- Mitchell Cooke
, Nicola Nicolici:
Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2060-2073 (2024) - Samuel Coulon, Tianyou Bao, Jiafeng Xie:
FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1684-1695 (2024) - Yuan Dai, Jingyuan Li, Qilong Zhu, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang:
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 505-518 (2024) - Nastaran Darabi, Maeesha Binte Hashem, Hongyi Pan, Ahmet Enis Çetin, Wilfred Gomes, Amit Ranjan Trivedi:
ADC/DAC-Free Analog Acceleration of Deep Neural Networks With Frequency Transformation. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 991-1003 (2024) - Tahesin Samira Delwar, Abrar Siddique, Unal Aras, Yang-Won Lee, Jee-Youl Ryu:
A μ-GA Oriented ANN-Driven: Parameter Extraction of 5G CMOS Power Amplifier. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1569-1577 (2024) - Charalampos Eleftheriadis, Georgios Chatzitsompanis, Georgios Karakonstantis:
Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design. IEEE Trans. Very Large Scale Integr. Syst. 32(2): 219-230 (2024) - Renas Ercan, Yunjia Xia, Yunyi Zhao, Rui C. V. Loureiro, Shufan Yang, Hubin Zhao:
An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 763-773 (2024) - Zipeng Fan, Sanqian Wang, Xueting Pu, Yuting Cong, Yuan Liu, Xiubao Sui, Qian Chen:
DLB-CNet: Difference Learning-Based Convolution Network for Building Change Detection. IEEE Trans. Very Large Scale Integr. Syst. 32(11): 2037-2045 (2024) - Fredrik Feyling, Hampus Malmberg, Carsten Wulff, Hans-Andrea Loeliger, Trond Ytterdal:
Design and Analysis of the Leapfrog Control-Bounded A/D Converter. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 79-88 (2024) - Bhaskar Gaur, Himanshu Thapliyal:
Novel Optimized Designs of Modulo 2n+1 Adder for Quantum Computing. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1759-1763 (2024) - Mizan Abraha Gebremicheal, Ibrahim M. Elfadel:
Secure Edge-Coded Signaling IoT Transceiver With Reduced Encryption Overhead. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1661-1671 (2024) - M. Ghashghai, M. B. Ghaznavi-Ghoushchi:
Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1792-1800 (2024) - Shouharda Ghosh, Pramod Kumar Meher, Dwaipayan Ray, Nithin V. George:
Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1409-1413 (2024) - Agnimesh Ghosh, Andrei Spelman, Tze Hin Cheung, Dhanashree Boopathy, Kari Stadius, Manil Dev Gomony, Mikko Valkama, Jussi Ryynänen, Marko Kosunen, Vishnu Unnikrishnan:
Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 4-15 (2024) - Shourya Gupta, Shuo Li, Benton H. Calhoun:
Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 190-194 (2024) - Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu:
Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 883-896 (2024) - Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu:
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 597-608 (2024) - Luchang He, Chenchen Xie, Zhao Han, Qingyu Wu, Houpeng Chen, Shibing Long, Xi Li, Zhitang Song:
A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow Typical Quiescent Current for Emerging Nonvolatile Memory. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1400-1408 (2024) - Luchang He, Chenchen Xie, Qingyu Wu, Siqiu Xu, Houpeng Chen, Xing Ding, Xi Li, Zhitang Song:
A Low-Cost Quadruple-Node-Upsets Resilient Latch Design. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1930-1939 (2024) - Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy:
Proteus: A Pipelined NTT Architecture Generator. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1228-1238 (2024) - Baoling Hong, Haikuo Shao, Zhongfeng Wang:
A Low Complexity Online Learning Approximate Message Passing Detector for Massive MIMO. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1273-1284 (2024) - Xiaolu Hou, Jakub Breier, Mladen Kovacevic:
Another Look at Side-Channel-Resistant Encoding Schemes. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1559-1563 (2024) - Xiao Hu, Zhihao Li, Zhongfeng Wang, Xianhui Lu:
ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption. IEEE Trans. Very Large Scale Integr. Syst. 32(4): 645-657 (2024) - Siji Huang, Debajit Basak, Yanhang Chen, Qifeng Huang, Yifei Fan, Jie Yuan:
An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1195-1204 (2024) - Qifeng Huang, Siji Huang, Yanhang Chen, Yifei Fan, Jie Yuan:
An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation. IEEE Trans. Very Large Scale Integr. Syst. 32(10): 1841-1851 (2024) - Haitong Huang, Cheng Liu, Xinghua Xue, Bo Liu, Huawei Li, Xiaowei Li:
MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1325-1335 (2024) - Yu-Kai Huang, Saul Rodriguez:
Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 55-67 (2024) - Pengcheng Huang, Yaohua Wang, Zhenyu Zhao, Daheng Yue:
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 137-149 (2024) - YaJuan Hui, Qingzhen Li, Leimin Wang, Cheng Liu, Deming Zhang, Xiangshui Miao:
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 497-504 (2024) - Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1336-1349 (2024)
