- 2017
- Marko S. Andjelkovic
, Milos Krstic, Rolf Kraemer:
An analysis of the operation and SET robustness of a CMOS pulse stretching circuit. DDECS 2017: 61-66 - Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Stephen Adeboye Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein:
From online fault detection to fault management in Network-on-Chips: A ground-up approach. DDECS 2017: 48-53 - Arash Barzinmehr, Suleyman Tosun:
Energy-aware application-specific topology generation for 3D Network-on-Chips. DDECS 2017: 84-87 - Saurabh Chaturvedi, Mladen Bozanic, Saurabh Sinha:
A 50 GHz SiGe BiCMOS active bandpass filter. DDECS 2017: 2-5 - Davide Dicorato, Petr Pfeifer, Heinrich Theodor Vierhaus:
Fault detection and self repair in Hsiao-code FEC circuits. DDECS 2017: 42-47 - Norbert Druml, Christoph Ehrenhöfer, Walter Bell, Christian Gailer, Hannes Plank, Thomas Herndl, Gerald Holweg:
A fast and flexible HW/SW co-processing framework for Time-of-Flight 3D imaging. DDECS 2017: 165-170 - Tino Flenker, Görschwin Fey:
Mapping abstract and concrete hardware models for design understanding. DDECS 2017: 16-21 - Andreas Furtig, Georg Glaeser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Hyun-Sek Lukas Lee, Gregor Nitsche, Markus Olbrich, Carna Radojicic, Fabian Speicher:
Novel metrics for Analog Mixed-Signal coverage. DDECS 2017: 97-102 - Ivo Hálecek, Petr Fiser, Jan Schmidt:
Are XORs in logic synthesis really necessary? DDECS 2017: 134-139 - Martin Hunek, Zdenek Plíva:
Design and optimisation of NiTi pressure gauge. DDECS 2017: 1-3 - Radek Isa, Jirí Matousek:
A novel architecture for LZSS compression of configuration bitstreams within FPGA. DDECS 2017: 171-176 - Ondrej Kachman, Marcel Baláz:
Firmware Update Manager: A remote firmware reprogramming tool for low-power devices. DDECS 2017: 88-91 - Matthias Kampmann, Sybille Hellebrand:
Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test. DDECS 2017: 35-41 - Madis Kerner, Kalle Tammemäe:
Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator. DDECS 2017: 92-95 - Lukás Kohútka, Viera Stopjaková:
Rocket Queue: New data sorting architecture for real-time systems. DDECS 2017: 207-212 - Asma Mkhinini, Paolo Maistri, Régis Leveugle, Rached Tourki:
HLS design of a hardware accelerator for Homomorphic Encryption. DDECS 2017: 178-183 - Felix Mühlbauer, Lukas Schröder, Mario Schölzel:
On hardware-based fault-handling in dynamically scheduled processors. DDECS 2017: 201-206 - Pawel Narczyk, Krzysztof Siwiec, Witold A. Pleskacz:
Analog front-end for precise human body temperature measurement. DDECS 2017: 67-72 - Ondrej Novák, Zdenek Plíva:
Logic testing with test-per-clock pattern loading and improved diagnostic abilities. DDECS 2017: 54-59 - Saya Ohira, Tetsuya Matsumura:
Design for three-dimensional sound processor using high-level synthesis. DDECS 2017: 190-193 - Mustafa Ozgul, Florian Deeg, Sebastian M. Sattler:
Mealy-to-moore transformation. DDECS 2017: 22-27 - Thomas Polzer, Florian Huemer, Andreas Steininger:
Measuring metastability using a time-to-digital converter. DDECS 2017: 116-121 - Sunil Satish Rao, Benjamin Prautsch, Ashish Shrivastava, Torsten Reich:
Body biasing for analog design: Practical experiences in 22 nm FD-SOI. DDECS 2017: 73-78 - Feim Ridvan Rasim, Canan Kocar, Sebastian M. Sattler:
Structure-preserving modeling of safety-critical combinational circuits. DDECS 2017: 109-114 - Andreas Rauchenecker, Robert Wille:
An efficient physical design of fully-testable BDD-based circuits. DDECS 2017: 6-11 - Patrick Russell, Jens Döge, Christoph Hoppe, Thomas B. Preußer, Peter Reichel, Peter Schneider:
Implementation of an asynchronous bundled-data router for a GALS NoC in the context of a VSoC. DDECS 2017: 195-200 - Oliver Schrape, Manuel Herrmann, Frank Winkler, Milos Krstic:
Routing approach for digital, differential bipolar designs using virtual fat-wire boundary pins. DDECS 2017: 122-126 - Michael Schwarz, Carlos Villarraga, Dominik Stoffel, Wolfgang Kunz:
Cycle-accurate software modeling for RTL verification of embedded systems. DDECS 2017: 103-108 - Miroslav Siro, Dominik Macko, Katarína Jelemenská:
PMS2UPF: An automated transition from ESL to RTL power-intent specification. DDECS 2017: 140-144 - Petr Socha, Vojtech Miskovský, Hana Kubátová, Martin Novotný:
Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. DDECS 2017: 184-189
