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Journal Articles
- 2014
[j7]Yi-Hao Zhang, Yue-Hong Shen, Min Dong, Yi-Min Jiang:
A method of batching conflict routings in shuffle-exchange networks. Theor. Comput. Sci. 522: 24-33 (2014)- 2008
- [j6]Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan:
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs. J. Comput. 3(3): 6-13 (2008) - 2003
- [j5]Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
:
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 756-769 (2003) - 2001
- [j4]Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng:
Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 416-425 (2001) - [j3]Yi-Min Jiang, Kwang-Ting Cheng:
Vector generation for power supply noise estimation and verification of deep submicron designs. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 329-340 (2001) - 2000
- [j2]Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng:
Estimation for maximum instantaneous current through supply lines for CMOS circuits. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 61-73 (2000) - 1994
- [j1]Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Youn-Long Lin:
Performance-driven interconnection optimization for microarchitecture synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 137-149 (1994)
Conference and Workshop Papers
- 2022
- [c14]Xiang Gao, Yi-Min Jiang, Lixin Shao, Pedja Raspopovic, Menno E. Verbeek, Manish Sharma, Vineet Rashingkar, Amit Jalota:
Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble. ISPD 2022: 195-202 - 2007
- [c13]Kaijian Shi, Zhian Lin, Yi-Min Jiang:
A Power Network Synthesis Method for Industrial Power Gating Designs. ISQED 2007: 362-367 - 2001
- [c12]Yi-Min Jiang, Han Young Koh, Kwang-Ting Cheng:
HRM - A Hierarchical Simulator for Full-Chip Power Network Reliability Analysis. ISQED 2001: 307-312 - [c11]Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng:
Delay testing considering crosstalk-induced effects. ITC 2001: 558-567 - 2000
- [c10]Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng:
Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. ICCAD 2000: 493-496 - [c9]Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng:
Dynamic Timing Analysis Considering Power Supply Noise Effects. ISQED 2000: 137-144 - 1999
- [c8]Yi-Min Jiang, Kwang-Ting Cheng:
Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices. DAC 1999: 760-765 - [c7]Yi-Min Jiang, Tak K. Young, Kwang-Ting Cheng:
VIP - an input pattern generator for indentifying critical voltage drop for deep sub-micron designs. ISLPED 1999: 156-161 - [c6]Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng:
Delay testing considering power supply noise effects. ITC 1999: 181-190 - 1998
- [c5]Yi-Min Jiang, Shi-Yu Huang, Kwang-Ting Cheng, Deborah C. Wang, ChingYen Ho:
A Hybrid Power Model for RTL Power Estimation. ASP-DAC 1998: 551-556 - [c4]Yi-Min Jiang, Kwang-Ting Cheng:
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. DATE 1998: 698-702 - [c3]Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng:
Estimation of maximum power supply noise for deep sub-micron designs. ISLPED 1998: 233-238 - 1997
- [c2]Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska:
Post-Layout Logic Restructuring for Performance Optimization. DAC 1997: 662-665 - 1992
- [c1]Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin:
Performance-driven interconnection optimization for microarchitecture synthesis. EURO-DAC 1992: 118-123
Coauthor Index
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