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2010 – 2019
- 2014
[c13]Kaijian Shi:
Message from conference general chair. SoCC 2014: iv-v- [e3]Kaijian Shi, Thomas Büchner, Danella Zhao, Ramalingam Sridhar:
27th IEEE International System-on-Chip Conference, SOCC 2014, Las Vegas, NV, USA, September 2-5, 2014. IEEE 2014, ISBN 978-1-4799-3378-5 [contents] - 2013
- [c12]Kaijian Shi, Nagi Naganathan:
Message from program chairs. SoCC 2013: 6 - [c11]Kaijian Shi:
Sleep transistor design in 28nm CMOS technology. SoCC 2013: 278-283 - [e2]Norbert Schuhmann, Kaijian Shi, Nagi Naganathan:
2013 IEEE International SOC Conference, Erlangen, Germany, September 4-6, 2013. IEEE 2013, ISBN 978-1-4799-1166-0 [contents] - 2012
- [j2]Shane Stelmach, Kaijian Shi, Anthony Hill:
Automation of Switch Insertion and Power Network Generation in 28 nm Power-Switched Designs. J. Low Power Electron. 8(5): 739-745 (2012) - [e1]Ramalingam Sridhar, Norbert Schuhmann, Kaijian Shi:
IEEE 25th International SOC Conference, SOCC 2012, Niagara Falls, NY, USA, September 12-14, 2012. IEEE 2012, ISBN 978-1-4673-1294-3 [contents] - 2011
- [c10]Kaijian Shi, David Tester:
Well tapping methodologies in power-gating design. SoCC 2011: 128-131 - 2010
- [c9]Kaijian Shi:
Low-power SOC implementation: What you need to know. SoCC 2010: 95
2000 – 2009
- 2008
- [j1]Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan:
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs. J. Comput. 3(3): 6-13 (2008) - [c8]Kaijian Shi:
Area and power-delay efficient state retention pulse-triggered flip-flops with scan and reset capabilities. ICCD 2008: 170-175 - 2007
- [b1]Michael Keating, David Flynn, Robert C. Aitken, Alan Gibbons, Kaijian Shi:
Low Power Methodology Manual - for System-on-Chip Design. Springer 2007, ISBN 978-0-387-71818-7, pp. I-XVI, 1-300 - [c7]Kaijian Shi, Zhian Lin, Yi-Min Jiang:
A Power Network Synthesis Method for Industrial Power Gating Designs. ISQED 2007: 362-367 - [c6]Kaijian Shi, Jingsong Li:
A wakeup rush current and charge-up time analysis method for programmable power-gating designs. SoCC 2007: 163-165 - 2006
- [c5]Kaijian Shi, David Howard:
Challenges in sleep transistor design and implementation in low-power designs. DAC 2006: 113-116 - 2005
- [c4]Thi Nguyen, Kaijian Shi:
Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs. ASAP 2005: 204-212 - [c3]Thi Nguyen, Kaijian Shi:
Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate Designs. SoCC 2005: 225-228 - [c2]Kaijian Shi, Hichem Belhadj:
A Clock Isolation Method For Complex SoC Designs. SoCC 2005: 251-256 - 2003
- [c1]Kaijian Shi, Graig Godwin:
Hybrid hierarchical timing closure methodology for a high performance and low power DSP. DAC 2003: 850-855
Coauthor Index
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