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2020 – today
- 2023
[c48]Guan-Sheng Wang, Chih-Yu Lin, Yu-Chee Tseng, Lan-Da Van:
A Multilayer Perceptron Model for Station Grouping in IEEE 802.11ah Networks. NOMS 2023: 1-5- 2022
- [j19]João B. O. Souza Filho, Lan-Da Van, Tzyy-Ping Jung, Paulo S. R. Diniz
:
Online Component Analysis, Architectures and Applications. Found. Trends Signal Process. 16(3-4): 224-429 (2022) - [c47]Rashid Ali, Ivan Surya Hutomo, Lan-Da Van, Yu-Chee Tseng:
A Skeleton-based View-Invariant Framework for Human Fall Detection in an Elevator. ICIT 2022: 1-6 - [c46]Albert Budi Christian, Chih-Yu Lin, Yu-Chee Tseng, Lan-Da Van, Wan-Hsun Hu, Chia-Hsuan Yu:
Accuracy-Time Efficient Hyperparameter Optimization Using Actor-Critic-based Reinforcement Learning and Early Stopping in OpenAI Gym Environment. IoTaIS 2022: 230-234 - [c45]Albert Budi Christian, Yu-Hsuan Wu, Chih-Yu Lin, Lan-Da Van, Yu-Chee Tseng:
Radar and Camera Fusion for Object Forecasting in Driving Scenarios. MCSoC 2022: 105-111 - 2021
- [j18]Lan-Da Van, Ling-Yan Zhang, Chun-Hao Chang, Kit-Lun Tong, Kun-Ru Wu, Yu-Chee Tseng:
Things in the air: tagging wearable IoT information on drone videos. Discov. Internet Things 1(1) (2021) - [j17]Lan-Da Van, You-Cheng Tu, Chi-Yuan Chang, Hsiang-Jen Wang, Tzyy-Ping Jung:
Hardware-Oriented Memory-Limited Online Artifact Subspace Reconstruction (HMO-ASR) Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 68(12): 3493-3497 (2021) - [c44]Albert Budi Christian, Chih-Yu Lin, Lan-Da Van, Yu-Chee Tseng:
Data Fusion Driven Lane-level Precision Data Transmission for V2X Road Applications. MCSoC 2021: 157-163 - [c43]Lan-Da Van, Tao-Jung Wang, Sing-Jia Tzeng, Tzyy-Ping Jung:
A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-Core CPU. MCSoC 2021: 171-177 - [c42]Tzu-An Huang, Sai-Keung Wong, Lan-Da Van:
Trajectory-Based Dynamic Handwriting Recognition Using Fusion Neural Network. TAAI 2021: 7-12 - [c41]Susanta Sharma, Allumallu Veera Venkata Susmitha, Lan-Da Van, Yu-Chee Tseng:
An Edge-Controlled Outdoor Autonomous UAV for Colorwise Safety Helmet Detection and Counting of Workers in Construction Sites. VTC Fall 2021: 1-5 - 2020
- [j16]Lan-Da Van, Yi-Bing Lin, Tsung-Han Wu, Tzu-Hsiang Chao:
Green Elevator Scheduling Based on IoT Communications. IEEE Access 8: 38404-38415 (2020) - [j15]Lan-Da Van, Yi-Bing Lin, Tsung-Han Wu, Yu-Chi Lin:
An Intelligent Elevator Development and Management System. IEEE Syst. J. 14(2): 3015-3026 (2020)
2010 – 2019
- 2019
- [j14]Lan-Da Van, Yi-Bing Lin, Tsung-Han Wu, Yun-Wei Lin, Syuan-Ru Peng, Lin-Hang Kao, Chun-Hao Chang:
PlantTalk: A Smartphone-Based Intelligent Hydroponic Plant Box. Sensors 19(8): 1763 (2019) - [c40]Lan-Da Van, Tsung-Che Lu, Tzyy-Ping Jung, Jo-Fu Wang:
Hardware-oriented Memory-limited Online Fastica Algorithm and Hardware Architecture for Signal Separation. ICASSP 2019: 1438-1442 - [c39]Lan-Da Van, Chun-Hao Chang, Kit-Lun Tong, Kun-Ru Wu, Ling-Yan Zhang, Yu-Chee Tseng:
Demo: Tagging IoT Data in a Drone View. MobiCom 2019: 70:1-70:3 - 2018
- [j13]Ching-Chieh Chiu, Lan-Da Van, Yu-Shu Lin:
Efficient Progressive Radiance Estimation Engine Architecture and Implementation for Progressive Photon Mapping. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(8): 2491-2502 (2018) - [c38]Lan-Da Van, Tsung-Che Lu, Pei-Yu Chen, Hari C. Reddy:
Type-4 2-D Diagonal and Four-Fold Rotational Symmetry Digital Filter Architectures. APCCAS 2018: 115-118 - [c37]Tsung-Che Lu, Chien-Liang Lin, Pei-Yu Chen, Lan-Da Van:
FPGA-Oriented Real-Time EMD-Based Breath Signal Processing System on ARM11 MPCore Platform. DSP 2018: 1-4 - 2017
- [c36]Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, I-Hung Khoo:
Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis. ASICON 2017: 726-729 - [c35]Pei-Yu Chen, Lan-Da Van, I-Hung Khoo, Hari C. Reddy:
New 2-D quadrantal- and diagonal-symmetry filter architectures using delta operator. ASICON 2017: 1133-1136 - [c34]Zone-Ze Wu, Cheng-Wei Wu, Lan-Da Van, Yu-Chee Tseng:
Qnalyzer: Queuing Recognition Using Accelerometer and Wi-Fi Signals. GLOBECOM 2017: 1-7 - [c33]Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, I-Hung Khoo:
New 2-D filter architectures with quadrantal symmetry and octagonal symmetry and their error analysis. MWSCAS 2017: 265-268 - [c32]Xin Zhang, Cheng-Wei Wu, Philippe Fournier-Viger, Lan-Da Van, Yu-Chee Tseng:
Analyzing students' attention in class using wearable devices. WoWMoM 2017: 1-9 - 2016
- [j12]Lan-Da Van, Po-Yen Huang, Tsung-Che Lu:
Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing. J. Signal Process. Syst. 82(1): 91-113 (2016) - [c31]Tsung-Han Wu, Chun-Hao Chang, Yun-Wei Lin, Lan-Da Van, Yi-Bing Lin:
Intelligent Plant Care Hydroponic Box Using IoTtalk. iThings/GreenCom/CPSCom/SmartData 2016: 398-401 - 2014
- [j11]I-Hung Khoo, Hari C. Reddy, Lan-Da Van, Chin-Teng Lin:
General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry. Multidimens. Syst. Signal Process. 25(4): 795-828 (2014) - [c30]Tsung-Che Lu, Pei-Yu Chen, Shih-Wei Yeh, Lan-Da Van:
Multiple stopping criteria and high-precision EMD architecture implementation for Hilbert-Huang transform. BioCAS 2014: 200-203 - [c29]Tsung-Che Lu, Shang Hwa Hsu, Sing-Jia Tzeng, Che-Ming Chang, Lan-Da Van:
Implementation of a human-centric GUI for next-generation intensive care unit. ICCE-TW 2014: 179-180 - [c28]Jun-Wei Qiu, Ting-Hui Chiang, Chi-Chung Lo, Li-Min Lin, Lan-Da Van, Yu-Chee Tseng, Yu-Tai Ching:
Continuous Human Location and Posture Tracking by Multiple Depth Sensors. iThings/GreenCom/CPSCom 2014: 155-160 - 2013
- [c27]Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, I-Hung Khoo:
Area-efficient 2-D digital filter architectures possessing diagonal and four-fold rotational symmetries. ICICS 2013: 1-5 - [c26]I-Hung Khoo, Hari C. Reddy, Lan-Da Van, Chin-Teng Lin:
Design of 2-D digital filters with almost quadrantal symmetric magnitude response without 1-D separable denominator factor constraint. MWSCAS 2013: 999-1002 - 2012
- [c25]I-Hung Khoo, Hari C. Reddy, Lan-Da Van, Chin-Teng Lin:
Delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the quadrantal symmetry. ISCAS 2012: 3190-3193 - 2011
- [j10]Pei-Yu Chen, Lan-Da Van, I-Hung Khoo, Hari C. Reddy, Chin-Teng Lin:
Power-Efficient and Cost-Effective 2-D Symmetry Filter Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(1): 112-125 (2011) - [j9]Lan-Da Van, Teng-Yao Sheu:
A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2211-2224 (2011) - [j8]Lan-Da Van, Di-You Wu, Chien-Shiun Chen:
Energy-Efficient FastICA Implementation for Biomedical Signal Separation. IEEE Trans. Neural Networks 22(11): 1809-1822 (2011) - [j7]Di-You Wu, Lan-Da Van:
Efficient Detection Algorithms for MIMO Communication Systems. J. Signal Process. Syst. 62(3): 427-442 (2011) - [c24]Tsung-Che Lu, Lan-Da Van, Chi-Sheng Lin, Chun-Ming Huang:
A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications. CICC 2011: 1-4
2000 – 2009
- 2009
- [j6]Jin-Hao Tu, Lan-Da Van:
Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers. IEEE Trans. Computers 58(10): 1346-1355 (2009) - [c23]Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, Chin-Teng Lin:
A New VLSI 2-D Fourfold-rotational-symmetry Filter Architecture Design. ISCAS 2009: 93-96 - [c22]I-Hung Khoo, Hari C. Reddy, Lan-Da Van, Chin-Teng Lin:
2-D Digital Filter Architectures without Global Broadcast and Some Symmetry Applications. ISCAS 2009: 952-955 - [c21]Teng-Yao Sheu, Lan-Da Van, Tzung-Rung Jung, Cheng-Wei Lin, Ting-Wei Chang:
Low Complexity Subdivision Algorithm to Approximate Phong Shading using Forward Difference. ISCAS 2009: 2373-2376 - 2008
- [j5]Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van:
Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 1058-1071 (2008) - [c20]Pei-Yu Chen, Lan-Da Van, Hari C. Reddy, Chin-Teng Lin:
A new VLSI 2-D diagonal-symmetry filter architecture design. APCCAS 2008: 320-323 - [c19]Tzung-Rung Jung, Lan-Da Van, Teng-Yao Sheu, Cheng-Wei Lin, Wai-Chi Fang:
Design of multi-mode depth buffer compression for 3D graphics system. ICME 2008: 789-792 - [c18]Chih-Wen Hsueh, Jen-Feng Chung, Lan-Da Van, Chin-Teng Lin:
Anticipatory access pipeline design for phased cache. ISCAS 2008: 2342-2345 - [c17]Chun-Chieh Huang, Shao-Hang Hung, Jen-Feng Chung, Lan-Da Van, Chin-Teng Lin:
Front-end amplifier of low-noise and tunable BW/gain for portable biomedical signal acquisition. ISCAS 2008: 2717-2720 - [c16]Tzung-Rung Jung, Lan-Da Van, Wai-Chi Fang, Teng-Yao Sheu:
Reconfigurable Depth Buffer Compression Design for 3D Graphics System. MUE 2008: 470-474 - [c15]Di-You Wu, Lan-Da Van:
A Grouped-Iterative Framework for MIMO Detection. VTC Fall 2008: 1-5 - 2007
- [j4]Min-An Song, Lan-Da Van, Sy-Yen Kuo:
Adaptive Low-Error Fixed-Width Booth Multipliers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(6): 1180-1187 (2007) - [j3]Lan-Da Van, Chin-Teng Lin, Yuan-Chu Yu:
VLSI Architecture for the Low-Computation Cycle and Power-Efficient Recursive DFT/IDFT Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(8): 1644-1652 (2007) - [c14]Chin-Teng Lin, Li-Wei Ko, Ken-Li Lin, Sheng-Fu Liang, Bor-Chen Kuo, I-Fang Chung, Lan-Da Van:
Classification of Driver's Cognitive Responses Using Nonparametric Single-trial EEG Analysis. ISCAS 2007: 2019-2023 - 2006
- [c13]Chin-Teng Lin, Yuan-Chu Yu, Lan-Da Van:
A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application. ISCAS 2006 - [c12]Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-Ming Huang:
A cost-effective reconfigurable accelerator for platform-based SOC design. ISCAS 2006 - [c11]Chun-Ming Huang, Kuen-Jong Lee, Chih-Chyau Yang, Wen-Hsiang Hu, Shi-Shen Wang, Jeng-Bin Chen, Chi-Shi Chen, Lan-Da Van, Chien-Ming Wu, Wei-Chang Tsai, Jing-Yang Jou:
Multi-Project System-on-Chip (MP-SoC): A Novel Test Vehicle for SoC Silicon Prototyping. SoCC 2006: 137-140 - 2005
- [j2]Lan-Da Van, Chih-Chyau Yang:
Generalized Low-Error Area-Efficient Fixed-Width Multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8): 1608-1619 (2005) - [c10]Hong-Yu Chao, Jia-Shung Wang, Juin-Long Lin, Kai-Chao Yang, Chien-Ming Wu, Chun-Ming Huang, Lan-Da Van:
High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS. ICME 2005: 89-92 - [c9]Min-An Song, Lan-Da Van, Chih-Chyau Yang, Shih-Chieh Chiu, Sy-Yen Kuo:
A framework for the design of error-aware power-efficient fixed-width Booth multipliers. ISCAS (1) 2005: 81-84 - 2004
- [c8]Lan-Da Van, Hsin-Fu Luo, Chien-Ming Wu, Wen-Hsiang Hu, Chun-Ming Huang, Wei-Chang Tsai:
A high-performance area-aware DSP processor architecture for video codecs. ICME 2004: 1499-1502 - [c7]Lan-Da Van, Chih-Chyau Yang:
High-speed area-efficient recursive DFT/IDFT architectures. ISCAS (3) 2004: 357-360 - 2002
- [j1]Lan-Da Van:
A new 2-D systolic digital filter architecture without global broadcast. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 477-486 (2002) - [c6]Lan-Da Van, Chih-Hong Chang:
Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR). ISCAS (1) 2002: 37-40 - [c5]Lan-Da Van, Sung-Huang Lee:
A generalized methodology for lower-error area-efficient fixed-width multipliers. ISCAS (1) 2002: 65-68 - 2001
- [c4]Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng:
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage. ISCAS (4) 2001: 794-797 - 2000
- [c3]Lan-Da Van, Chih-Chun Tang, Shing Tenqchen, Wu-Shiung Feng:
A new VLSI architecture without global broadcast for 2-D digital filters. ISCAS 2000: 547-550
1990 – 1999
- 1999
- [c2]Lan-Da Van, Shing Tenqchen, Chia-Hsun Chang, Wu-Shiung Feng:
A tree-systolic array of DLMS adaptive filter. ICASSP 1999: 1253-1256 - [c1]Lan-Da Van, Shuenn-Shyang Wang, Shing Tenqchen, Wu-Shiung Feng, Bor-Shenn Jeng:
Design of a lower-error fixed-width multiplier for speech processing application. ISCAS (3) 1999: 130-133
Coauthor Index
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