"Cost-Effective and Variable-Channel FastICA Hardware Architecture and ..."

Lan-Da Van, Po-Yen Huang, Tsung-Che Lu (2016)

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DOI: 10.1007/S11265-015-0988-2

access: closed

type: Journal Article

metadata version: 2020-03-12

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Lan-Da Van, Po-Yen Huang, Tsung-Che Lu:
Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing. J. Signal Process. Syst. 82(1): 91-113 (2016)

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