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ORCIDJiajia Li 0002
Person information
- affiliation: University of California at San Diego, La Jolla, CA, USA
Other persons with the same name
- Jiajia Li (aka: Jia-Jia Li, Jia-jia Li, JiaJia Li) — disambiguation page
- Jiajia Li 0001
![[0000-0003-1270-4147]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-1270-4147")
— North Carolina State University, Raleigh, NC, USA (and 2 more)
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Books and Theses
- 2017
[b1]Jiajia Li:
Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality. University of California, San Diego, USA, 2017
Journal Articles
- 2020
- [j9]Kwangsoo Han, Andrew B. Kahng, Jiajia Li:
Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 478-491 (2020) - 2019
- [j8]Hamed Fatemi, Andrew B. Kahng, Hyein Lee, Jiajia Li, José Pineda de Gyvez:
Enhancing sensitivity-based power reduction for an industry IC design context. Integr. 66: 96-111 (2019) - 2018
- [j7]Sorin Dobre, Andrew B. Kahng, Jiajia Li:
Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 855-868 (2018) - [j6]Alex Kahng, Andrew B. Kahng, Hyein Lee, Jiajia Li:
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1459-1472 (2018) - 2017
- [j5]Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li:
Revisiting 3DIC benefit with multiple tiers. Integr. 58: 226-235 (2017) - [j4]Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Trading Accuracy for Energy in Stochastic Circuit Design. ACM J. Emerg. Technol. Comput. Syst. 13(3): 47:1-47:30 (2017) - [j3]Kristof Blutman, Hamed Fatemi, Ajay Kapoor, Andrew B. Kahng, Jiajia Li, José Pineda de Gyvez:
Logic Design Partitioning for Stacked Power Domains. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3045-3056 (2017) - 2015
- [j2]Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez:
An Improved Methodology for Resilient Design Implementation. ACM Trans. Design Autom. Electr. Syst. 20(4): 66:1-66:26 (2015) - [j1]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath, Bongil Park:
Optimization of Overdrive Signoff in High-Performance and Low-Power ICs. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1552-1556 (2015)
Conference and Workshop Papers
- 2017
- [c15]Kristof Blutman, Hamed Fatemi, Andrew B. Kahng, Ajay Kapoor, Jiajia Li, José Pineda de Gyvez:
Floorplan and placement methodology for improved energy reduction in stacked power-domain design. ASP-DAC 2017: 444-449 - 2016
- [c14]Kun Young Chung, Andrew B. Kahng, Jiajia Li:
Comprehensive optimization of scan chain timing during late-stage IC implementation. DAC 2016: 61:1-61:6 - [c13]Kwangsoo Han, Andrew B. Kahng, Jiajia Li:
Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. DATE 2016: 61-66 - [c12]Andrew B. Kahng, Jiajia Li, Lutong Wang:
Improved flop tray-based design implementation for power reduction. ICCAD 2016: 20 - [c11]Andrew B. Kahng, Hyein Lee, Jiajia Li:
Measuring progress and value of IC implementation technology. ICCAD 2016: 27 - [c10]Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li:
Revisiting 3DIC Benefit with Multiple Tiers. SLIP 2016: 6:1-6:8 - 2015
- [c9]Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee:
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. DAC 2015: 26:1-26:6 - [c8]Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs. ICCAD 2015: 178-185 - [c7]Sorin Dobre, Andrew B. Kahng, Jiajia Li:
Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes. ICCAD 2015: 854-860 - 2014
- [c6]Andrew B. Kahng, Hyein Lee, Jiajia Li:
Horizontal benchmark extension for improved assessment of physical CAD research. ACM Great Lakes Symposium on VLSI 2014: 27-32 - [c5]Andrew B. Kahng, Seokhyeong Kang, Jiajia Li:
A new methodology for reduced cost of resilience. ACM Great Lakes Symposium on VLSI 2014: 157-162 - [c4]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li:
NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation. ISQED 2014: 504-509 - 2013
- [c3]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li, Siddhartha Nath:
Optimization of overdrive signoff. ASP-DAC 2013: 344-349 - [c2]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li:
Reliability-constrained die stacking order in 3DICs under manufacturing variability. ISQED 2013: 16-23 - [c1]Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li:
Toward quantifying the IC design value of interconnect technology improvements. SLIP 2013: 1-6
Coauthor Index
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