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ORCIDKwangsoo Han
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2020 – today
- 2020
[j3]Kwangsoo Han
, Andrew B. Kahng, Jiajia Li:
Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 478-491 (2020)
2010 – 2019
- 2018
- [b1]Kwangsoo Han:
IC Physical Design Methodologies for Advanced Process Nodes. University of California, San Diego, USA, 2018 - [c13]Kwangsoo Han, Andrew B. Kahng, Christopher Moyes, Alex Zelikovsky:
A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions. SLIP@DAC 2018: 2:1-2:8 - [c12]Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh:
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. ISPD 2018: 10-17 - 2017
- [j2]Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng:
Benchmarking of Mask Fracturing Heuristics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 170-183 (2017) - [j1]Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1075-1088 (2017) - [c11]Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. DAC 2017: 51:1-51:6 - [c10]Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu:
Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. ICCAD 2017: 667-674 - [c9]Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang:
Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes. ISQED 2017: 104-110 - 2016
- [c8]Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Mulong Luo:
Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products. ASP-DAC 2016: 697-704 - [c7]Kwangsoo Han, Andrew B. Kahng, Jiajia Li:
Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. DATE 2016: 61-66 - 2015
- [c6]Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee:
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction. DAC 2015: 26:1-26:6 - [c5]Kwangsoo Han, Andrew B. Kahng, Hyein Lee:
Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. DAC 2015: 68:1-68:6 - [c4]Kwangsoo Han, Andrew B. Kahng, Hyein Lee:
Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. ICCAD 2015: 867-873 - [c3]Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Vaishnav Srinivas:
Clock clustering and IO optimization for 3D integration. SLIP 2015: 1-8 - 2014
- [c2]Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath:
OCV-aware top-level clock tree optimization. ACM Great Lakes Symposium on VLSI 2014: 33-38 - [c1]Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria:
Benchmarking of mask fracturing heuristics. ICCAD 2014: 246-253
Coauthor Index
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