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2020 – today
- 2021
[j11]Wang-Dauh Tseng
:
A Cascaded Multicasting Architecture for Test Data Compression. J. Electron. Test. 37(2): 205-214 (2021)
2010 – 2019
- 2019
- [j10]Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai:
Multi-Scan Architecture with Scan Chain Disabling Technique for Capture Power Reduction. J. Inf. Sci. Eng. 35(4): 839-849 (2019) - 2018
- [j9]Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai:
Asymmetry dual-LFSR reseeding for low power BIST. Integr. 60: 272-276 (2018) - [c10]Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai:
Bipolar Dual-LFSR Reseeding for Low-Power Testing. DSC 2018: 1-7 - 2012
- [j8]Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang:
$2^{n}$ Pattern Run-Length for Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(4): 644-648 (2012) - [c9]Lung-Jen Lee, Chia-Cheng He, Wang-Dauh Tseng:
Deterministic ATPG for Low Capture Power Testing. MTV 2012: 24-29 - [c8]Lung-Jen Lee, Wang-Dauh Tseng, Wen-Ting Yang:
Dual-LFSR Reseeding for Low Power Testing. MTV 2012: 30-34 - [c7]Lung-Jen Lee, Wang-Dauh Tseng, Wei-Shun Chen:
Two-Way Multicasting for Test Data Compression. MTV 2012: 60-64 - 2010
- [j7]Wang-Dauh Tseng, Lung-Jen Lee:
Test Data Compression Using Multi-dimensional Pattern Run-length Codes. J. Electron. Test. 26(3): 393-400 (2010) - [j6]Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin:
Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction. IET Comput. Digit. Tech. 4(4): 317-324 (2010)
2000 – 2009
- 2009
- [c6]Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu:
Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing. Asian Test Symposium 2009: 111-116 - [c5]Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee:
A Multi-dimensional Pattern Run-Length Method for Test Data Compression. Asian Test Symposium 2009: 325-330 - 2008
- [j5]Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin:
Power Reduction during Scan Testing Based on Multiple Capture Technique. IEICE Trans. Electron. 91-C(5): 798-805 (2008) - 2007
- [j4]Wang-Dauh Tseng:
Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing. J. Electron. Test. 23(1): 75-84 (2007) - [j3]I-Shyan Hwang, Ren-Yuan Cheng, Wang-Dauh Tseng:
A novel dynamic Multiple Ring-based Local Restoration for point-to-multipoint multicast traffic in WDM mesh networks. Photonic Netw. Commun. 14(1): 23-33 (2007) - [c4]Wang-Dauh Tseng, Lung-Jen Lee:
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering. MTV 2007: 15-21 - 2006
- [j2]I-Shyan Hwang, Meng-Yuan Tu, Wang-Dauh Tseng, Zen-Der Shyu:
A novel dynamic fault restoration mechanism using cluster allocation approach in WDM mesh networks. Comput. Commun. 29(18): 3921-3932 (2006) - 2002
- [c3]Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen:
Printed circuit board routing and package layout codesign. APCCAS (1) 2002: 155-158
1990 – 1999
- 1999
- [j1]Wang-Dauh Tseng, Kuochen Wang:
Fuzzy-based CMOS circuit partitioning in built-in current testing. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 116-120 (1999) - 1997
- [c2]Wang-Dauh Tseng, Kuochen Wang:
Fuzzy-based circuit partitioning in built-in current testing. ASP-DAC 1997: 397-400 - 1996
- [c1]Wang-Dauh Tseng, Kuochen Wang:
Testable Design and Testing of MCMs Based on Multifrequency Scan. Asian Test Symposium 1996: 75-
Coauthor Index
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