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ORCIDPo-Han Wang 0001
Person information
- affiliation: National Taiwan University, Department of Computer Science and Information Engineering, Taipei, Taiwan
Other persons with the same name
- Po-Han Peter Wang
![[0000-0002-6359-2109]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-6359-2109")
(aka: Po-Han Wang 0002) — University of California at San Diego, La Jolla, CA, USA
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2010 – 2019
- 2018
[c7]Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang:
Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures. DAC 2018: 112:1-112:6- 2017
- [j3]Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang:
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. IEEE Comput. Archit. Lett. 16(2): 127-131 (2017) - [c6]Li-Wei Shieh, Kun-Chih Chen, Hsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang:
Enabling fast preemption via Dual-Kernel support on GPUs. ASP-DAC 2017: 121-126 - [c5]Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung:
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. ISPASS 2017: 127-128 - 2016
- [c4]Po-Han Wang, Cheng-Hsuan Li, Chia-Lin Yang:
Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture. DAC 2016: 5:1-5:6 - 2014
- [c3]Po-Han Wang, Gen-Hong Liu, Jen-Chieh Yeh, Tse-Min Chen, Hsu-Yao Huang, Chia-Lin Yang, Shih-Lien Liu, James Greensky:
Full system simulation framework for integrated CPU/GPU architecture. VLSI-DAT 2014: 1-4 - 2012
- [c2]Po-Han Wang, Chien-Wei Lo, Chia-Lin Yang, Yu-Jung Cheng:
A cycle-level SIMT-GPU simulation framework. ISPASS 2012: 114-115 - 2011
- [j2]Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen, Yu-Jung Cheng:
Power gating strategies on GPUs. ACM Trans. Archit. Code Optim. 8(3): 13:1-13:25 (2011) - 2010
- [c1]Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang:
PM-COSYN: PE and memory co-synthesis for MPSoCs. DATE 2010: 1590-1595
2000 – 2009
- 2009
- [j1]Po-Han Wang, Yen-Ming Chen, Chia-Lin Yang, Yu-Jung Cheng:
A Predictive Shutdown Technique for GPU Shader Processors. IEEE Comput. Archit. Lett. 8(1): 9-12 (2009)
Coauthor Index
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