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Jakub Janicki
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Journal Articles
- 2015
- [j4]Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1050-1062 (2015) - 2014
- [j3]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 167 (2014) - 2013
- [j2]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1776-1786 (2013) - 2012
- [j1]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1894-1907 (2012)
Conference and Workshop Papers
- 2023
- [c10]Manoj Devendhiran, Jakub Janicki, Szczepan Urban, Manish Sharma, Jayant D'Souza:
Predicting the Resolution of Scan Diagnosis. ITC 2023: 303-309 - 2022
- [c9]Soumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson:
Industry Evaluation of Reversible Scan Chain Diagnosis. ITC 2022: 420-426 - 2020
- [c8]Jakub Janicki, Grzegorz Mrugalski, Artur Stelmach, Szczepan Urban:
Scan Chain Diagnosis-Driven Test Response Compactor. ATS 2020: 1-6 - 2019
- [c7]Yu Huang, Jakub Janicki, Szczepan Urban:
Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution. ETS 2019: 1-6 - 2014
- [c6]Maciej Trawka, Grzegorz Mrugalski, Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jakub Janicki, Jerzy Tyszer:
High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs. ATS 2014: 74-80 - 2013
- [c5]Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles:
EDT bandwidth management - Practical scenarios for large SoC designs. ITC 2013: 1-10 - 2012
- [c4]Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski:
Bandwidth-aware test compression logic for SoC designs. ETS 2012: 1-6 - 2011
- [c3]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki:
Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium 2011: 267-272 - [c2]Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC 2011: 1-9 - 2010
- [c1]Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer:
Dynamic channel allocation for higher EDT compression in SoC designs. ITC 2010: 265-274
Coauthor Index
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