"Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs"."

Jakub Janicki et al. (2014)

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DOI: 10.1109/TCAD.2013.2292631

access: closed

type: Journal Article

metadata version: 2020-09-24

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Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 167 (2014)

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