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Journal Articles
- 2024
[j7]Sandeep Sharma
, Saket Gupta, Mohd Zuhaib, Vijay Bhuria, Hasmat Malik, Abdulaziz Almutairi, Asyraf Afthanorhan, Mohammad Asef Hossaini:
A Comprehensive Review on STATCOM: Paradigm of Modeling, Control, Stability, Optimal Location, Integration, Application, and Installation. IEEE Access 12: 2701-2729 (2024)- [j6]Udit Mittal, Uma Nangia, Narender Kumar Jain, Saket Gupta:
Optimal power flow solution using a learning-based sine-cosine algorithm. J. Supercomput. 80(11): 15974-16012 (2024) - 2016
- [j5]Saket Gupta, Carl Monzel, Daniel S. Reed, Yifei Zhang, Mark Winter, Myron Buer:
Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7): 1014-1022 (2016) - 2014
- [j4]Saket Gupta, Sachin S. Sapatnekar:
Variation-Aware Variable Latency Design. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1106-1117 (2014) - 2013
- [j3]Sparsh Mittal, Saket Gupta, Ankush Mittal:
BioinQA: metadata-based multi-document QA system for addressing the issues in biomedical domain. Int. J. Data Min. Model. Manag. 5(1): 37-56 (2013) - [j2]Saket Gupta, Sachin S. Sapatnekar:
Employing circadian rhythms to enhance power and reliability. ACM Trans. Design Autom. Electr. Syst. 18(3): 38:1-38:23 (2013) - 2012
- [j1]Saket Gupta, Sachin S. Sapatnekar:
Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2104-2117 (2012)
Conference and Workshop Papers
- 2018
- [c7]Balaji Narasimham, Saket Gupta, Daniel S. Reed, J. K. Wang, Nick Hendrickson, Hasan Taufique:
Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs. IRPS 2018: 4 - 2015
- [c6]Balaji Narasimham, Jung K. Wang, Narayana Vedula, Saket Gupta, Brandon Bartz, Carl Monzel, Indranil Chatterjee, Bharat L. Bhuva, Ronald D. Schrimpf, Robert A. Reed:
Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs. IRPS 2015: 2 - 2012
- [c5]Saket Gupta, Sachin S. Sapatnekar:
GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. ASP-DAC 2012: 271-276 - [c4]Saket Gupta, Sachin S. Sapatnekar:
BTI-aware design using variable latency units. ASP-DAC 2012: 775-780 - [c3]Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim:
Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. CICC 2012: 1-4 - [c2]Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar:
Circuit reliability: From Physics to Architectures: Embedded tutorial paper. ICCAD 2012: 243-246 - 2010
- [c1]Saket Gupta, Sachin S. Sapatnekar:
Current source modeling in the presence of body bias. ASP-DAC 2010: 199-204
Coauthor Index
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