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ORCIDMitsuru Shiozaki
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2020 – today
- 2023
[j13]Mitsuru Shiozaki, Takeshi Sugawara
, Takeshi Fujino:
Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 281-293 (2023)- 2021
- [j12]Kota Yoshida, Mitsuru Shiozaki, Shunsuke Okura, Takaya Kubota, Takeshi Fujino:
Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(1): 152-161 (2021) - [j11]Mitsuru Shiozaki, Takeshi Fujino:
Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF. J. Cryptogr. Eng. 11(3): 201-212 (2021) - [j10]Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino:
Deep learning side-channel attack against hardware implementations of AES. Microprocess. Microsystems 87: 103383 (2021) - 2020
- [c17]Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino:
Exploring Effect of Residual Electric Charges on Cryptographic Circuits. ASHES@CCS 2020: 57-66 - [c16]Mitsuru Shiozaki, Yohei Hori, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino:
Cause Analysis Method of Entropy Loss in Physically Unclonable Functions. ISCAS 2020: 1-5 - [c15]Kota Yoshida, Takaya Kubota, Shunsuke Okura, Mitsuru Shiozaki, Takeshi Fujino:
Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator. ISCAS 2020: 1-5 - [i4]Mitsuru Shiozaki, Yohei Hori, Takeshi Fujino:
Entropy Estimation of Physically Unclonable Functions. IACR Cryptol. ePrint Arch. 2020: 1284 (2020)
2010 – 2019
- 2019
- [c14]Mitsuru Shiozaki, Takeshi Fujino:
Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF. ASHES@CCS 2019: 13-21 - [c13]Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino:
Deep Learning Side-Channel Attack Against Hardware Implementations of AES. DSD 2019: 261-268 - [c12]Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino:
Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis. FCCM 2019: 318 - 2018
- [c11]Shunsuke Okura, Ryota Ishiki, Masayoshi Shirahata, Takaya Kubota, Mitsuru Shiozaki, Kenichiro Ishikawa, Isao Takayanagi, Takeshi Fujino:
A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF. ISPACS 2018: 54-59 - 2017
- [j9]Takeshi Fujino, Takaya Kubota, Mitsuru Shiozaki:
Tamper-resistant cryptographic hardware. IEICE Electron. Express 14(2): 20162004 (2017) - [c10]Mitsuru Shiozaki, Takaya Kubota, Masashi Nakano, Yuuki Nakazawa, Takeshi Fujino:
Malicious CAN-message attack against advanced driving assistant system. HOST 2017: 158 - 2015
- [j8]Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino:
Reversing stealthy dopant-level circuits. J. Cryptogr. Eng. 5(2): 85-94 (2015) - [c9]Mitsuru Shiozaki, Takaya Kubota, Tsunato Nakai, Akihiro Takeuchi, Takashi Nishimura, Takeshi Fujino:
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. ISCAS 2015: 1462-1465 - 2014
- [j7]Koichi Shimizu, Daisuke Suzuki, Toyohiro Tsurumaru, Takeshi Sugawara, Mitsuru Shiozaki, Takeshi Fujino:
Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(1): 264-274 (2014) - [j6]Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino:
Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(1): 275-283 (2014) - [j5]Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino:
On measurable side-channel leaks inside ASIC design primitives. J. Cryptogr. Eng. 4(1): 59-73 (2014) - [c8]Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino:
Reversing Stealthy Dopant-Level Circuits. CHES 2014: 112-126 - [c7]Tsunato Nakai, Megumi Shibatani, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino:
Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks. ISCAS 2014: 2547-2550 - [i3]Mitsuru Shiozaki, Ryohei Hori, Takeshi Fujino:
Diffusion Programmable Device : The device to prevent reverse engineering. IACR Cryptol. ePrint Arch. 2014: 109 (2014) - [i2]Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino:
Reversing Stealthy Dopant-Level Circuits. IACR Cryptol. ePrint Arch. 2014: 508 (2014) - 2013
- [c6]Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino:
On Measurable Side-Channel Leaks Inside ASIC Design Primitives. CHES 2013: 159-178 - [c5]Masato Taniguchi, Mitsuru Shiozaki, Hiroshi Kubo, Takeshi Fujino:
A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications. GCCE 2013: 525-527 - [i1]Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino:
On Measurable Side-Channel Leaks inside ASIC Design Primitives. IACR Cryptol. ePrint Arch. 2013: 579 (2013) - 2012
- [j4]Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino:
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. IEICE Trans. Electron. 95-C(4): 468-477 (2012) - [c4]Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino:
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. DSD 2012: 735-738 - 2011
- [c3]Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino:
Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL. HOST 2011: 28-33 - [c2]Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino:
The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement. ISCAS 2011: 2325-2328
2000 – 2009
- 2007
- [c1]Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda:
12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique. ISSCC 2007: 180-595 - 2006
- [j3]Mitsuru Shiozaki, Mamoru Sasaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda:
20GHz uniform-phase uniform-amplitude standing-wave clock distribution. IEICE Electron. Express 3(2): 11-16 (2006) - 2005
- [j2]Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata:
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique. IEICE Trans. Electron. 88-C(6): 1233-1240 (2005) - [j1]Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata:
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors. J. Robotics Mechatronics 17(4): 463-468 (2005)
Coauthor Index
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