default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDASHES@CCS 2019: London, UK
- Chip-Hong Chang, Ulrich Rührmair, Daniel E. Holcomb, Patrick Schaumont
:
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, ASHES@CCS 2019, London, UK, November 15, 2019. ACM 2019, ISBN 978-1-4503-6839-1
Keynotes
- François-Xavier Standaert:
Towards an Open Approach to Side-Channel Resistant Authenticated Encryption. 1
Full Papers
- Mathieu Gross, Nisha Jacob, Andreas Zankl, Georg Sigl:
Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC. 3-12 - Mitsuru Shiozaki, Takeshi Fujino:
Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF. 13-21 - Aurélien Vasselle, Philippe Maurine, Maxime Cozzi:
Breaking Mobile Firmware Encryption through Near-Field Side-Channel Analysis. 23-32 - Keyvan Ramezanpour, Paul Ampadu, William Diehl:
Fault Intensity Map Analysis with Neural Network Key Distinguisher. 33-42 - Florian Unterstein, Nisha Jacob, Neil Hanley, Chongyan Gu, Johann Heyszl:
SCA Secure and Updatable Crypto Engines for FPGA SoC Bitstream Decryption. 43-53 - Sahan Bandara, Michel A. Kinsy:
Adaptive Caches as a Defense Mechanism Against Cache Side-Channel Attacks. 55-64 - Leonid Azriel, Ran Ginosar, Avi Mendelson:
SoK: An Overview of Algorithmic Methods in IC Reverse Engineering. 65-74 - Yuqiao Zhang, Pinchen Cui, Ziqi Zhou, Ujjwal Guin:
TGA: An Oracle-less and Topology-Guided Attack on Logic Locking. 75-83 - Bodo Selmke, Florian Hauschild, Johannes Obermaier:
Peak Clock: Fault Injection into PLL-Based Systems via Clock Manipulation. 85-94 - Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata, Shoei Nashimoto, Daisuke Suzuki:
A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. 95-100 - Chongyan Gu, Chip-Hong Chang, Weiqiang Liu, Neil Hanley, Jack Miskelly, Máire O'Neill:
A Large Scale Comprehensive Evaluation of Single-Slice Ring Oscillator and PicoPUF Bit Cells on 28nm Xilinx FPGAs. 101-106
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-19 20:50 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
