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2020 – today
- 2023
[b1]Mathieu Gross:
Remote Security Threats and Protection of Modern FPGA-SoC Architectures / Mathieu Etienne André Gross ; Gutachter: Georg Sigl, Walter Stechele ; Betreuer: Georg Sigl. Technical University of Munich, Germany, 2023- [c5]Mathieu Gross, Jonas Krautter, Dennis Gnad, Michael Gruber, Georg Sigl, Mehdi B. Tahoori:
FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU. ASP-DAC 2023: 358-364 - [i1]Mathieu Gross, Robert Kunzelmann
, Georg Sigl:
CPU to FPGA Power Covert Channel in FPGA-SoCs. IACR Cryptol. ePrint Arch. 2023: 429 (2023) - 2022
- [j3]Mathieu Gross, Nisha Jacob, Andreas Zankl, Georg Sigl:
Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC. J. Cryptogr. Eng. 12(2): 181-196 (2022) - [j2]Mathieu Gross, Konrad Hohentanner, Stefan Wiehler, Georg Sigl:
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM. ACM Trans. Reconfigurable Technol. Syst. 15(1): 5:1-5:26 (2022) - 2021
- [j1]Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl:
Beyond Cache Attacks: Exploiting the Bus-based Communication Structure for Powerful On-Chip Microarchitectural Attacks. ACM Trans. Embed. Comput. Syst. 20(2): 17:1-17:23 (2021)
2010 – 2019
- 2019
- [c4]Mathieu Gross, Nisha Jacob, Andreas Zankl, Georg Sigl:
Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC. ASHES@CCS 2019: 3-12 - 2018
- [c3]Georg Sigl, Mathieu Gross, Michael Pehl:
Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips. ESSCIRC 2018: 12-17 - 2017
- [c2]Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl:
Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips. ISVLSI 2017: 284-289 - [c1]Johanna Sepúlveda, Mathieu Gross, Andreas Zankl, Georg Sigl:
Towards trace-driven cache attacks on Systems-on-Chips - exploiting bus communication. ReCoSoC 2017: 1-7
Coauthor Index
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