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ORCIDBenjamin Stefan Devlin
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2010 – 2019
- 2013
[j4]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments. IEICE Trans. Electron. 96-C(4): 518-527 (2013)- 2012
- [j3]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling. IEICE Trans. Electron. 95-C(4): 546-554 (2012) - [c7]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. ASYNC 2012: 150-157 - [c6]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation. COOL Chips 2012: 1-3 - 2011
- [j2]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. IEEE J. Solid State Circuits 46(11): 2500-2513 (2011) - [c5]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC 2011: 75-76 - [c4]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system. ICECS 2011: 53-56 - [c3]Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA. ISLPED 2011: 3-8 - 2010
- [j1]Benjamin Stefan Devlin, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1319-1328 (2010) - [c2]Kunihiro Asada, Makoto Ikeda, Benjamin Stefan Devlin, Taku Sogabe:
Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging. DFT 2010: 3
2000 – 2009
- 2009
- [c1]Benjamin Stefan Devlin, MyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA. ESSCIRC 2009: 156-159
Coauthor Index
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