"A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS."

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada (2011)

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DOI: 10.1109/ASPDAC.2011.5722288

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
A gate-level pipelined 2.97GHz Self Synchronous FPGA in 65nm CMOS. ASP-DAC 2011: 75-76

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