"A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance ..."

Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada (2011)

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DOI: 10.1109/JSSC.2011.2164024

access: closed

type: Journal Article

metadata version: 2020-08-30

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Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation. IEEE J. Solid State Circuits 46(11): 2500-2513 (2011)

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