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Benoît Dupont de Dinechin

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2020 – today

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2023
[c50]
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Orégane Desrentes, Benoît Dupont de Dinechin, Florent de Dinechin:
Exact Fused Dot Product Add Operators. ARITH 2023: 151-158
[c49]
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Orégane Desrentes, Benoît Dupont de Dinechin, Julien Le Maire:
Exact Dot Product Accumulate Operators for 8-bit Floating-Point Deep Learning. DSD 2023: 642-649
[c48]
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Benoît Dupont de Dinechin, Julien Hascoët, Orégane Desrentes:
In-Place Multicore SIMD Fast Fourier Transforms. HPEC 2023: 1-6
2022
[c47]
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Orégane Desrentes, Diana Resmerita, Benoît Dupont de Dinechin:
A Posit8 Decompression Operator for Deep Neural Network Inference. CoNGA 2022: 14-30
[c46]
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Benoît Dupont de Dinechin:
Computing In-Place FFTs with SIMD Lane Slicing. HPEC 2022: 1-7
[p1]
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Benoît Dupont de Dinechin:
SSA Form and Code Generation. SSA-based Compiler Design 2022: 243-256
2021
[j8]
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Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, Sergio Saponara, Benoît Dupont de Dinechin:
Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities. IEEE Signal Process. Mag. 38(1): 97-110 (2021)
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Benoît Dupont de Dinechin:
Engineering a Manycore Processor for Edge Computing. MECO 2021: 1
[c44]
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Diana Resmerita, Rodrigo Cabral Farias, Benoît Dupont de Dinechin, Lionel Fillatre:
Distortion Approximation of a Compressed Softmax Layer. SSP 2021: 491-495
2020
[j7]
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Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge:
Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks. Perform. Evaluation 143: 102124 (2020)
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Matheus Schuh, Claire Maiza, Joël Goossens, Pascal Raymond, Benoît Dupont de Dinechin:
A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory. RTSS 2020: 283-295

2010 – 2019

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2019
[c42]
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Benoît Dupont de Dinechin:
Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor. DAC 2019: 154
[c41]
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Amaury Graillat, Claire Maiza, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin:
Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip. RTNS 2019: 61-69
2018
[j6]
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Georgia Giannopoulou, Peter Poplavko, Dario Socci, Pengcheng Huang, Nikolay Stoimenov, Paraskevas Bourgos, Lothar Thiele, Marius Bozga, Saddek Bensalem, Sylvain Girbal, Madeleine Faugère, Romain Soulat, Benoît Dupont de Dinechin:
DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems. Des. Autom. Embed. Syst. 22(1-2): 141-181 (2018)
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Amaury Graillat, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin:
Parallel code generation of synchronous programs for a many-core architecture. DATE 2018: 1139-1142
[c39]
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Hugo Miomandre, Julien Hascoët, Karol Desnos, Kevin J. M. Martin, Benoît Dupont de Dinechin, Jean-François Nezan:
Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures. PARMA-DITAM@HiPEAC 2018: 51-56
[c38]
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Julien Hascoet, Benoît Dupont de Dinechin, Karol Desnos, Jean-François Nezan:
A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore. HPEC 2018: 1-7
[c37]
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Benoît Dupont de Dinechin:
Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus. NOCS 2018: 25:1
2017
[c36]
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Julien Hascoet, Karol Desnos, Jean-François Nezan, Benoît Dupont de Dinechin:
Hierarchical Dataflow Model for efficient programming of clustered manycore processors. ASAP 2017: 137-142
[c35]
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Alvise Rigo, Christian Pinto, Kevin Pouget, Daniel Raho, Denis Dutoit, Pierre-Yves Martinez, Chris Doran, Luca Benini, Iakovos Mavroidis, Manolis Marazakis, Valeria Bartsch, Guy Lonsdale, Antoniu Pop, John Goodacre, Annaik Colliot, Paul M. Carpenter, Petar Radojkovic, Dirk Pleiter, Dominique Drouin, Benoît Dupont de Dinechin:
Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach. DSD 2017: 486-493
[c34]
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Julien Hascoët, Benoît Dupont de Dinechin, Pierre Guironnet de Massas, Minh Quan Ho:
Asynchronous one-sided communications and synchronizations for a clustered manycore processor. ESTIMedia 2017: 51-60
[c33]
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Benoît Dupont de Dinechin, Amaury Graillat:
Network-on-chip service guarantees on the kalray MPPA-256 bostan processor. AISTECS@HiPEAC 2017: 35-40
[c32]
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Minh Quan Ho, Christian Obrecht, Bernard Tourancheau, Benoît Dupont de Dinechin, Julien Hascoet:
Improving 3D lattice boltzmann method stencil with asynchronous transfers on many-core processors. IPCCC 2017: 1-9
[c31]
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Benoît Dupont de Dinechin, Amaury Graillat:
Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor. NoCArc@MICRO 2017: 10:1-10:6
2016
[j5]
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Georgia Giannopoulou, Nikolay Stoimenov, Pengcheng Huang, Lothar Thiele, Benoît Dupont de Dinechin:
Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources. Real Time Syst. 52(4): 399-449 (2016)
[c30]
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Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin:
Optimal and fast throughput evaluation of CSDF. DAC 2016: 160:1-160:6
2015
[c29]
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Selma Saidi, Rolf Ernst, Sascha Uhrig, Henrik Theiling, Benoît Dupont de Dinechin:
The shift to multicores in real-time and safety-critical systems. CODES+ISSS 2015: 220-229
[c28]
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Julien Hascoet, Jean-François Nezan, Andrew Ensor, Benoît Dupont de Dinechin:
Implementation of a Fast Fourier transform algorithm onto a manycore processor. DASIP 2015: 1-7
[c27]
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Benoît Dupont de Dinechin:
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor. Hot Chips Symposium 2015: 1-27
[c26]
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Minh Quan Ho, Bernard Tourancheau, Christian Obrecht, Benoît Dupont de Dinechin, Jérôme Reybert:
MPI communication on MPPA Many-core NoC: design, modeling and performance issues. PARCO 2015: 113-122
2014
[j4]
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Benoît Dupont de Dinechin, Alix Munier Kordon:
Converging to periodic schedules for cyclic scheduling problems with resources and deadlines. Comput. Oper. Res. 51: 227-236 (2014)
[c25]
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Benoît Dupont de Dinechin:
Using the SSA-Form in a Code Generator. CC 2014: 1-17
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Benoît Dupont de Dinechin, Duco van Amstel, Marc Poulhiès, Guillaume Lager:
Time-critical computing on a single-chip massively parallel processor. DATE 2014: 1-6
[c23]
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Benoît Dupont de Dinechin, Yves Durand, Duco van Amstel, Alexandre Ghiti:
Guaranteed Services of the NoC of a Manycore Processor. NoCArc@MICRO 2014: 11-16
2013
[j3]
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Alix Munier Kordon, Fadi Kacem, Benoît Dupont de Dinechin, Lucian Finta:
Scheduling an interval ordered precedence graph with communication delays and a limited number of processors. RAIRO Oper. Res. 47(1): 73-87 (2013)
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Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin:
Periodic schedules for Cyclo-Static Dataflow. ESTIMedia 2013: 105-114
[c21]
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Benoît Dupont de Dinechin, Renaud Ayrignac, Pierre-Edouard Beaucamps, Patrice Couvert, Benoit Ganne, Pierre Guironnet de Massas, François Jacquet, Samuel Jones, Nicolas Morey Chaisemartin, Frédéric Riss, Thierry Strudel:
A clustered manycore processor architecture for embedded and accelerated applications. HPEC 2013: 1-6
[c20]
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Pascal Aubry, Pierre-Edouard Beaucamps, Frédéric Blanc, Bruno Bodin, Sergiu Carpov, Loïc Cudennec, Vincent David, Philippe Dore, Paul Dubrulle, Benoît Dupont de Dinechin, François Galea, Thierry Goubier, Michel Harrand, Samuel Jones, Jean-Denis Lesage, Stéphane Louise, Nicolas Morey Chaisemartin, Thanh-Hai Nguyen, Xavier Raynaud, Renaud Sirdey:
Extended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor. ICCS 2013: 1624-1633
[c19]
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Benoît Dupont de Dinechin, Pierre Guironnet de Massas, Guillaume Lager, Clément Léger, Benjamin Orgogozo, Jérôme Reybert, Thierry Strudel:
A Distributed Run-Time Environment for the Kalray MPPA^®-256 Integrated Manycore Processor. ICCS 2013: 1654-1663
2012
[j2]
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Dibyendu Das, Benoît Dupont de Dinechin, Ramakrishna Upadrasta:
Efficient liveness computation using merge sets and DJ-graphs. ACM Trans. Archit. Code Optim. 8(4): 27:1-27:18 (2012)
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Bruno Bodin, Alix Munier Kordon, Benoît Dupont de Dinechin:
K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph. ICSAMOS 2012: 152-159
2011
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Sid Ahmed Ali Touati, Frederic Brault, Karine Deschinkel, Benoît Dupont de Dinechin:
Efficient Spilling Reduction for Software Pipelined Loops in Presence of Multiple Register Types in Embedded VLIW Processors. ACM Trans. Embed. Comput. Syst. 10(4): 47:1-47:25 (2011)
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Nicolas Brunie, Florent de Dinechin, Benoît Dupont de Dinechin:
A mixed-precision fused multiply and add. ACSCC 2011: 165-169
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Benoit Boissinot, Florian Brandner, Alain Darte, Benoît Dupont de Dinechin, Fabrice Rastello:
A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs. APLAS 2011: 137-154

2000 – 2009

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2009
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Benoit Boissinot, Alain Darte, Fabrice Rastello, Benoît Dupont de Dinechin, Christophe Guillon:
Revisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency. CGO 2009: 114-125
2008
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Benoit Boissinot, Sebastian Hack, Daniel Grund, Benoît Dupont de Dinechin, Fabrice Rastello:
Fast liveness checking for ssa-form programs. CGO 2008: 35-44
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Benoît Dupont de Dinechin:
Inter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors. Euro-Par 2008: 370-381
2006
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Florent Blachot, Benoît Dupont de Dinechin, Guillaume Huard:
SCAN: A Heuristic for Near-Optimal Software Pipelining. Euro-Par 2006: 289-298
2005
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Jean-Michel Muller, Arnaud Tisserand, Benoît Dupont de Dinechin, Christophe Monat:
Division by Constant for the ST100 DSP Microprocessor. IEEE Symposium on Computer Arithmetic 2005: 124-130
2000
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Benoît Dupont de Dinechin, François de Ferrière, Christophe Guillon, Artour Stoutchinin:
Code generator optimizations for the ST120 DSP-MCU core. CASES 2000: 93-102

1990 – 1999

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1999
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Benoît Dupont de Dinechin:
Extending Modulo Scheduling with Memory Reference Merging. CC 1999: 274-287
1997
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Robert W. Numrich, Jon L. Steidel, Brian H. Johnson, Benoît Dupont de Dinechin, Gary Elsesser, Greg Fischer, Tom MacDonald:
Definition of the F^-- Extension to Fortran 90. LCPC 1997: 292-306
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Benoît Dupont de Dinechin:
A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops. LCPC 1997: 382-393
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Benoît Dupont de Dinechin:
A Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops. PaCT 1997: 189-200
1996
[c5]
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Benoît Dupont de Dinechin:
Parametric Computation of Margins and of Minimum Cumulative Register Lifetime Dates. LCPC 1996: 231-245
1995
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Benoît Dupont de Dinechin:
Insertion Scheduling: An Alternative to List Scheduling for Modulo Schedulers. LCPC 1995: 31-45
1994
[c3]
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Benoît Dupont de Dinechin:
An Introduction to Simplex Scheduling. IFIP PACT 1994: 327-330
1992
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Benoît Dupont de Dinechin:
StaCS: a Static Control Superscalar architecture. MICRO 1992: 282-291
1991
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Benoît Dupont de Dinechin:
A ultra fast Euclidean division algorithm for prime memory systems. SC 1991: 56-65

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