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2020 – today
- 2024
[c38]Felipe Lisboa Malaquias, Mihail Asavoae, Florian Brandner:
Leveraging Reusable Code and Proofs to Design Complex DRAM Controllers - A Case Study. DSD 2024: 298-305- [c37]Florient Champenois, Florian Brandner, Thierry Grandpierre, Etienne Borde, Abraham Suissa, Laurent Georges:
Multi-Criteria Optimization of Distributed Real-Time Network Topologies. ISORC 2024: 1-11 - 2023
- [j10]Felipe Lisboa Malaquias
, Mihail Asavoae, Florian Brandner:
A formal framework to design and prove trustworthy memory controllers. Real Time Syst. 59(4): 664-704 (2023) - [c36]Felipe Lisboa Malaquias, Mihail Asavoae, Florian Brandner:
From the Standards to Silicon: Formally Proved Memory Controllers. NFM 2023: 295-311 - 2022
- [j9]Florian Brandner, Camille Noûs:
Precise, efficient, and context-sensitive cache analysis. Real Time Syst. 58(1): 36-84 (2022) - [j8]Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, Mathieu Jan:
Formal modeling and verification for amplification timing anomalies in the superscalar TriCore architecture. Int. J. Softw. Tools Technol. Transf. 24(3): 415-440 (2022) - [c35]Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, Mathieu Jan:
The Role of Causality in a Formal Definition of Timing Anomalies. RTCSA 2022: 91-102 - [c34]Felipe Lisboa Malaquias, Mihail Asavoae, Florian Brandner:
A Coq Framework for More Trustworthy DRAM Controllers. RTNS 2022: 140-150 - [p3]Florian Brandner, Diego Novillo:
Propagating Information Using SSA. SSA-based Compiler Design 2022: 95-106 - 2021
- [c33]Benjamin Binder, Mihail Asavoae, Belgacem Ben Hedia, Florian Brandner, Mathieu Jan:
Is This Still Normal? Putting Definitions of Timing Anomalies to the Test. RTCSA 2021: 139-148 - 2020
- [j7]Farouk Hebbache, Florian Brandner, Mathieu Jan, Laurent Pautet:
Work-conserving dynamic time-division multiplexing for multi-criticality systems. Real Time Syst. 56(2): 124-170 (2020) - [c32]Benjamin Binder, Mihail Asavoae, Florian Brandner, Belgacem Ben Hedia, Mathieu Jan:
Scalable Detection of Amplification Timing Anomalies for the Superscalar TriCore Architecture. FMICS 2020: 151-169 - [c31]Florian Brandner, Camille Noûs:
Precise and Efficient Analysis of Context-Sensitive Cache Conflict Sets. RTNS 2020: 44-55
2010 – 2019
- 2019
- [c30]Farouk Hebbache, Florian Brandner, Mathieu Jan, Laurent Pautet:
Arbitration-Induced Preemption Delays. ECRTS 2019: 19:1-19:22 - 2018
- [j6]Amine Naji, Sahar Abbaspour, Florian Brandner, Mathieu Jan:
Analysis of preemption costs for the stack cache. Real Time Syst. 54(3): 700-744 (2018) - [c29]Farouk Hebbache, Mathieu Jan, Florian Brandner, Laurent Pautet:
Shedding the Shackles of Time-Division Multiplexing. RTSS 2018: 456-468 - [e2]Florian Brandner:
18th International Workshop on Worst-Case Execution Time Analysis, WCET 2018, July 3, 2018, Barcelona, Spain. OASIcs 63, Schloss Dagstuhl - Leibniz-Zentrum für Informatik 2018, ISBN 978-3-95977-073-6 [contents] - 2017
- [c28]Kameswar Rao Vaddina, Florian Brandner, Gérard Memmi, Pierre Jouvelot:
Experimental energy profiling of energy-critical embedded applications. SoftCOM 2017: 1-6 - [c27]Florian Brandner, Amine Naji:
Worst-Case Execution Time Analysis of Predicated Architectures. WCET 2017: 6:1-6:13 - [c26]Karel De Vogeleer, Kameswar Rao Vaddina, Florian Brandner, Pierre Jouvelot, Gérard Memmi:
Modeling the energy consumption of programs: Thermal aspects and energy/frequency convexity rule (invited paper). WCSP 2017: 1-10 - 2016
- [c25]Amine Naji, Florian Brandner:
Eager Stack Cache Memory Transfers. WCET 2016: 5:1-5:11 - 2015
- [c24]Sahar Abbaspour, Florian Brandner, Amine Naji, Mathieu Jan:
Efficient context switching for the stack cache: implementation and analysis. RTNS 2015: 119-128 - 2014
- [j5]Florian Brandner, Alexander Jordan:
Refinement of worst-case execution time bounds by graph pruning. Comput. Lang. Syst. Struct. 40(3-4): 155-170 (2014) - [j4]Florian Brandner, Stefan Hepp, Alexander Jordan:
Criticality: static profiling for real-time programs. Real Time Syst. 50(3): 377-410 (2014) - [j3]Quentin Colombet, Florian Brandner, Alain Darte:
Studying Optimal Spilling in the Light of SSA. ACM Trans. Archit. Code Optim. 11(4): 47:1-47:26 (2014) - [c23]Stefan Hepp, Florian Brandner:
Splitting functions into single-entry regions. CASES 2014: 17:1-17:10 - [c22]I. Kotleas, D. Humphreys, Rasmus Bo Sørensen, Evangelia Kasapaki, Florian Brandner, Jens Sparsø:
A loosely synchronizing asynchronous router for TDM-scheduled NOCs. NOCS 2014: 151-158 - [c21]Sahar Abbaspour, Alexander Jordan, Florian Brandner:
Lazy Spilling for a Time-Predictable Stack Cache: Implementation and Analysis. WCET 2014: 83-92 - [e1]Florian Brandner, Tom Vander Aa:
Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems, ODES@CGO 2014, Orlando, Florida, USA, February 15, 2014. ACM 2014, ISBN 978-1-4503-2595-0 [contents] - 2013
- [j2]Florian Brandner, Quentin Colombet:
Elimination of parallel copies using code motion on data dependence graphs. Comput. Lang. Syst. Struct. 39(1): 25-47 (2013) - [j1]Florian Brandner, Viktor Pavlu, Andreas Krall:
Automatic generation of compiler backends. Softw. Pract. Exp. 43(2): 207-240 (2013) - [c20]Sahar Abbaspour, Florian Brandner, Martin Schoeberl:
A time-predictable stack cache. ISORC 2013: 1-8 - [c19]Alexander Jordan, Florian Brandner, Martin Schoeberl:
Static analysis of worst-case stack cache behavior. RTNS 2013: 55-64 - [p2]Florian Brandner, R. Nigel Horspool, Andreas Krall:
DSP Instruction Set Simulation. Handbook of Signal Processing Systems 2013: 945-974 - 2012
- [c18]Martin Schoeberl, Florian Brandner, Jens Sparsø, Evangelia Kasapaki:
A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems. NOCS 2012: 152-160 - [c17]Florian Brandner, Martin Schoeberl:
Static routing in symmetric real-time network-on-chips. RTNS 2012: 61-70 - [c16]Florian Brandner, Stefan Hepp, Alexander Jordan:
Static profiling of the worst-case in real-time programs. RTNS 2012: 101-110 - [c15]Florian Brandner, Quentin Colombet:
Copy elimination on data dependence graphs. SAC 2012: 1916-1918 - 2011
- [c14]Benoit Boissinot, Florian Brandner, Alain Darte, Benoît Dupont de Dinechin, Fabrice Rastello:
A Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs. APLAS 2011: 137-154 - [c13]Quentin Colombet, Florian Brandner, Alain Darte:
Studying optimal spilling in the light of SSA. CASES 2011: 25-34 - [c12]Martin Schoeberl, Pascal Schleuniger, Wolfgang Puffitsch, Florian Brandner, Christian W. Probst:
Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach. PPES 2011: 11-21 - [c11]Florian Brandner, Viktor Pavlu, Andreas Krall:
Modeling application-specific processors for embedded systems. GI-Jahrestagung 2011: 327 - 2010
- [c10]Florian Brandner:
Completeness of automatically generated instruction selectors. ASAP 2010: 175-182 - [c9]Michael Bebenita, Florian Brandner, Manuel Fähndrich, Francesco Logozzo, Wolfram Schulte, Nikolai Tillmann, Herman Venter:
SPUR: a trace-based JIT compiler for CIL. OOPSLA 2010: 708-725 - [c8]Martin Schoeberl, Florian Brandner, Jan Vitek:
RTTM: real-time transactional memory. SAC 2010: 326-333 - [p1]Florian Brandner, R. Nigel Horspool, Andreas Krall:
DSP Instruction Set Simulation. Handbook of Signal Processing Systems 2010: 679-705
2000 – 2009
- 2009
- [c7]Florian Brandner, Tommy Thorn, Martin Schoeberl:
Embedded JIT Compilation with CACAO on YARI. ISORC 2009: 63-70 - [c6]Peter Molnar, Andreas Krall, Florian Brandner:
Stack allocation of objects in the CACAO virtual machine. PPPJ 2009: 153-161 - [c5]Florian Brandner:
Precise simulation of interrupts using a rollback mechanism. SCOPES 2009: 71-80 - 2008
- [c4]Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann, Albrecht Kadlec:
Generalized instruction selection using SSA-graphs. LCTES 2008: 31-40 - 2007
- [c3]Florian Brandner, Dietmar Ebner, Andreas Krall:
Compiler generation from structural architecture descriptions. CASES 2007: 13-22 - [c2]Dietmar Ebner, Florian Brandner, Andreas Krall:
Leveraging Predicated Execution for Multimedia Processing. ESTIMedia 2007: 85-90 - 2006
- [c1]Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner:
Effective compiler generation by architecture description. LCTES 2006: 145-152
Coauthor Index
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last updated on 2024-11-20 21:59 CET by the dblp team
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