default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDASIP 2015: Krakow, Poland
- 2015 Conference on Design and Architectures for Signal and Image Processing, DASIP 2015, Krakow, Poland, September 23-25, 2015. IEEE 2015, ISBN 978-1-4673-7738-6
Session 1: Image processing on embedded systems
- Marc Reichenbach
, Maximilian Kasparek, Mohammad Alawieh, Konrad Häublein, Dietmar Fey:
Real-time correlation for locating systems utilizing heterogeneous computing architectures. 1-8 - Jens Rettkowski, David Gburek, Diana Göhringer:
Robot navigation based on an efficient combination of an extended A∗ algorithm, bird's eye view and image stitching. 1-8 - Mateusz Komorkiewicz, Tomasz Kryjak, Katarzyna Chuchacz-Kowalczyk, Pawel Skruch, Marek Gorgon:
FPGA based system for real-time structure from motion computation. 1-7
Session 2: Processing architectures for biomedical signal and image processing
- Paolo Meloni, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo:
Exploring custom heterogeneous MPSoCs for real-time neural signal decoding. 1-8 - Amina El Hassen, Aymeric Histace, Mehdi Terosiet, Olivier Romain:
FPGA-based detection of QRS complexes in ECG signal. 1-7
Demo night
- Kevin J. M. Martin, Yvan Eustache, Jean-Philippe Diguet, Thanh Dinh Ngo, Emmanuel Casseau, Yaset Oliva:
Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms. 1-2 - Benno Stabernack, Jan Moller, Jan Hahlbeck, Jens Brandenburg:
Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support. 1-2
Session 3: Application-specific processors
- Sebastian Hesselbarth, Gregor Schewior, Holger Blume:
Fast and accurate power estimation for application-specific instruction set processors using FPGA emulation. 1-7 - Shanshan Wang, Chenglong Xiao, Wanjun Liu, Emmanuel Casseau, Xiao Yang:
Selecting most profitable instruction-set extensions using ant colony heuristic. 1-7
Session 4: Signal processing on reconfigurable architectures
- Guillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet:
Hardware implementation of a soft cancellation decoder for polar codes. 1-8 - Guy Wassi, Sylvain Iloga, Olivier Romain, Bertrand Granado:
FPGA-based real-time MFCC extraction for automatic audio indexing on FM broadcast data. 1-6 - Sajjad Nouri, Waqar Hussain, Jari Nurmi:
Implementation of IEEE-802.11a/g receiver blocks on a coarse-grained reconfigurable array. 1-8
Session 5: Image tiling and denoising
- Vítor Schwambach, Sébastien Cleyet-Merle, Alain Issard, Stéphane Mancini:
Image tiling for embedded applications with non-linear constraints. 1-8 - Sampsa Sarjanoja, Jani Boutellier, Jari Hannuksela:
BM3D image denoising using heterogeneous computing platforms. 1-8 - Mladen Skelin, Marc Geilen, Francky Catthoor, Sverre Hendseth:
Worst-case latency analysis of SDF-based parametrized dataflow MoCs. 1-6 - Stephan Werner, Bernhard Stiehle, Jürgen Becker:
Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip. 1-6 - Ercan Kalali, Ilker Hamzaoglu:
FPGA implementations of HEVC Inverse DCT using high-level synthesis. 1-6 - Andrianiaina Ravelomanantsoa, Hassan Rabah, Amar Rouane:
Fast and efficient signals recovery for deterministic compressive sensing: Applications to biosignals. 1-6 - Mohamed Mourad Hafidhi, Emmanuel Boutillon, Chris Winstead:
Reducing the impact of internal upsets inside the correlation process in GPS Receivers. 1-5 - Jordane Lorandel, Jean-Christophe Prévotet, Maryline Hélard:
Dynamic power evaluation of LTE wireless baseband processing on FPGA. 1-6 - Mourad Dridi, Mohamed Mourad Hafidhi, Chris Winstead, Emmanuel Boutillon:
Reliable NCO carrier generators for GPS receivers. 1-5
Session 6: Parallel implementations of HEVC and FFT for embedded multi-/manycore systems
- Jens Brandenburg, Benno Stabernack:
Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architectures. 1-8 - Maurizio Masera, Lorenzo Re Fiorentin, Maurizio Martina, Guido Masera, Enrico Masala:
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding. 1-6 - Julien Hascoet, Jean-François Nezan, Andrew Ensor, Benoît Dupont de Dinechin:
Implementation of a Fast Fourier transform algorithm onto a manycore processor. 1-7
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-04 20:52 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
