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ORCIDAbdel Ejnioui
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2010 – 2019
- 2015
[c33]Rawad N. Al-Haddad, Rashad S. Oreifej, Ramtin Zand
, Abdel Ejnioui, Ronald F. DeMara:
Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics. NATW 2015: 23-32- 2013
- [j8]Abdel Ejnioui, Carlos E. Otero, Luis Daniel Otero:
Prioritisation of software requirements using grey relational analysis. Int. J. Comput. Appl. Technol. 47(2/3): 100-109 (2013) - [j7]Abdel Ejnioui, Carlos E. Otero, Ivica Kostanic:
A stochastic approach for evaluating quality of service in wireless cellular networks. Int. J. Wirel. Mob. Comput. 6(3): 201-208 (2013) - [c32]Abdel Ejnioui, Carlos E. Otero, Abrar A. Qureshi:
Formalizing the design of embedded software using sequence diagrams and abstract state machines. RIIT 2013: 71-76 - [c31]Abdel Ejnioui, Carlos E. Otero, Abrar A. Qureshi:
Engineering graphic user interfaces with protected content. SysCon 2013: 31-36 - [c30]Jeffrey A. McDougall, Luis Daniel Otero, Juan Avendano, Abdel Ejnioui:
System analysis methods in emergency systems. SysCon 2013: 818-823 - [c29]Rana Haber, Adrian M. Peter, Carlos E. Otero, Ivica Kostanic, Abdel Ejnioui:
A support vector machine for terrain classification in on-demand deployments of wireless sensor networks. SysCon 2013: 841-846 - 2012
- [c28]Abdel Ejnioui, Carlos E. Otero, Luis Daniel Otero:
A simulation-based fuzzy multi-attribute decision making for prioritizing software requirements. RIIT 2012: 37-42 - 2011
- [j6]Angel R. Otero, Abdel Ejnioui, Carlos E. Otero, Gurvirender Tejay:
Evaluation of Information Security Controls in Organizations by Grey Relational Analysis. Int. J. Dependable Trust. Inf. Syst. 2(3): 36-54 (2011)
2000 – 2009
- 2009
- [c27]Abdel Ejnioui:
Runtime Adaptation in Reconfigurable System-on-Chips. ICPP Workshops 2009: 535-541 - 2008
- [c26]Abdel Ejnioui, Paul Bao:
A parallel architecture for GFA modeling in video coding. CIT 2008: 595-600 - [c25]Abdel Ejnioui, Paul Bao:
A Parallel Array to Accelerate GFA Modeling in Video Coding. ERSA 2008: 252-258 - 2007
- [j5]Ronald F. DeMara, Yili Tseng, Abdel Ejnioui:
Tiered Algorithm for Distributed Process Quiescence and Termination Detection. IEEE Trans. Parallel Distributed Syst. 18(11): 1529-1538 (2007) - [c24]Abdel Ejnioui, Paul Bao:
Hardware Acceleration of the Generalized Finite Automata Algorithm. CDES 2007: 140-146 - [c23]Abdel Ejnioui:
Prototyping of a Two-Phase Micropipeline on FPGAs. ERSA 2007: 138-146 - [c22]Abdel Ejnioui, Paul Bao:
Hardware Architectures for the Generalized Finite Automata Algorithm. ICECS 2007: 721-724 - [c21]Abdel Ejnioui:
FPGA Prototyping of a Two-Phase Self-Oscillating Micropipeline. ISVLSI 2007: 437-438 - 2006
- [c20]Anuja Jayraj Thakkar, Abdel Ejnioui:
Pipelining of double precision floating point division and square root operations. ACM Southeast Regional Conference 2006: 488-493 - [c19]Heng Tan, Ronald F. DeMara, Anuja Jayraj Thakkar, Abdel Ejnioui, Jason Sattler:
Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study. ERSA 2006: 253-256 - [c18]Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui:
Synthesis of Pipelined SRSL Circuits. ISVLSI 2006: 71-76 - [c17]Abdelhalim Alsharqawi, Abdel Ejnioui:
Clockless Pipelining for Coarse Grain Datapaths. VLSI Design 2006: 749-753 - 2005
- [c16]Abdel Ejnioui, Ronald F. DeMara:
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices. ERSA 2005: 196-202 - [c15]Abdelhalim Alsharqawi, Abdel Ejnioui:
SRSL pipelining of coarse-grain datapaths. ICECS 2005: 1-4 - [c14]Rashad S. Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui:
Pipeline synthesis of SRSL circuits. ICECS 2005: 1-4 - [c13]Abdelhalim Alsharqawi, Abdel Ejnioui:
Synthesis of Self-Resetting Stage Logic Pipelines. ISVLSI 2005: 260-262 - 2004
- [c12]Abdel Ejnioui, Abdelhalim Alsharqawi:
Pipeline-Level Control of Self-Resetting Pipelines. DSD 2004: 342-349 - [c11]Abdel Ejnioui, Abdelhalim Alsharqawi:
Self-resetting stage logic pipelines. ACM Great Lakes Symposium on VLSI 2004: 174-177 - [c10]Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui:
Control and Data Flow Graph Extraction for High-Level Synthesis. ISVLSI 2004: 187-192 - [c9]Abdel Ejnioui, Abdelhalim Alsharqawi:
Pipeline Design Based on Self-Resetting Stage Logic. ISVLSI 2004: 254-257 - [c8]Abdel Ejnioui, Abdelkader Rhiati:
A Reconfigurable Memory Management Core for Java Applications. ISVLSI 2004: 309-312 - 2003
- [j4]Abdel Ejnioui, N. Ranganathan:
Multiterminal net routing for partial crossbar-based multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 11(1): 71-78 (2003) - [j3]Abdel Ejnioui, N. Ranganathan:
Routing on field-programmable switch matrices. IEEE Trans. Very Large Scale Integr. Syst. 11(2): 283-287 (2003) - [c7]W. Kuang, J. S. Yuan, Abdel Ejnioui:
Supply Voltage Scalable System Design Using Self-Timed Circuits. ISVLSI 2003: 161-166 - 2002
- [c6]K. Sitaraman, N. Ranganathan, Abdel Ejnioui:
A VLSI Architecture for Object Recognition Using Tree Matching. ASAP 2002: 325-334 - 2001
- [j2]Abdel Ejnioui, N. Ranganathan:
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 407-410 (2001) - 2000
- [c5]Abdel Ejnioui, N. Ranganathan:
Design Partitioning on Single-Chip Emulation Systems. VLSI Design 2000: 234-239 - [c4]Abdel Ejnioui, N. Ranganathan:
Routing on Switch Matrix Multi-FPGA Systems. VLSI Design 2000: 248-253
1990 – 1999
- 1999
- [j1]Vamsi Krishna, N. Ranganathan, Abdel Ejnioui:
A tree-matching chip. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 277-280 (1999) - [c3]Abdel Ejnioui, N. Ranganathan:
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. FPGA 1999: 176-185 - 1996
- [c2]Vamsi Krishna, Abdel Ejnioui, N. Ranganathan:
A tree matching chip. VLSI Design 1996: 280-285 - 1995
- [c1]Abdel Ejnioui, N. Ranganathan:
Systolic algorithms for tree pattern matching. ICCD 1995: 650-702
Coauthor Index
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