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ORCID24th NATW 2015: Johnson City, NY, USA
- 24th IEEE North Atlantic Test Workshop, NATW 2015, Johnson City, NY, USA, May 11-13, 2015. IEEE 2015, ISBN 978-1-4673-7417-0
- Mohamed Hanafy
, Hazem Said, Ayman M. Wahba:
Complete Properties Extraction from Simulation Traces for Assertions Auto-generation. 1-6 - Ramesh C. Tekumalla:
Clock Domain Imbalances and Their Impact on Test Architecture. 7-10 - Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski:
Hybrid Hierarchical and Modular Tests for SoC Designs. 11-16 - Amin Vali, Nicola Nicolici:
Satisfiability-Based Analysis of Failing Traces during Post-silicon Debug. 17-22 - Rawad N. Al-Haddad, Rashad S. Oreifej, Ramtin Zand, Abdel Ejnioui, Ronald F. DeMara:
Adaptive Mitigation of Radiation-Induced Errors and TDDB in Reconfigurable Logic Fabrics. 23-32 - Jennifer Dworak, Ping Gui, Qutaiba Khasawneh:
An Industrial Case Study: PaRent (Parallel & Concurrent) Testing for Complex Mixed-Signal Devices. 33-38 - Swati Chakraborty, Duncan M. Hank Walker:
At-Speed Path Delay Test. 39-42 - Sameer Chillarige, S. Virdi, Anil Malik, Krishna Chakravadhanula, Vivek Chickermane, Joe Swenton, G. Vandling:
A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures. 43-48 - Baohu Li, Vishwani D. Agrawal:
Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing. 49-54 - Huiting Zhang, Vishwani D. Agrawal:
SoC TAM Design to Minimize Test Application Time. 55-60
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