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ORCIDRamesh C. Tekumalla
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2010 – 2019
- 2018
[c20]M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla:
Innovative practices on memory test practice. VTS 2018: 1- 2015
- [c19]Ramesh C. Tekumalla:
Clock Domain Imbalances and Their Impact on Test Architecture. NATW 2015: 7-10 - 2014
- [c18]Ramesh C. Tekumalla, Prakash Krishnamoorthy:
Local Repair Signature Handling for Repairable Memories. NATW 2014: 1-5 - [c17]Surbhi Bansal, Aviansh Mendhalkar, Ramesh C. Tekumalla:
On Handling Memory Scan Chains. NATW 2014: 6-10 - [c16]Ramesh C. Tekumalla, Prakash Krishnamoorthy:
On-chip Clock Testing and Frequency Measurement. NATW 2014: 11-14 - [c15]Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane:
Innovative practices session 1C: Existing/emerging low power techniques. VTS 2014: 1 - 2013
- [c14]Prakash Krishnamoorthy, Ramesh C. Tekumalla:
Power aware transformation of bandlimited signals. SoCC 2013: 178-183 - [c13]Prakash Krishnamoorthy, Ramesh C. Tekumalla:
Quotient prediction for low power division. SoCC 2013: 273-277 - [c12]Charutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene:
Innovative practices session 2C: Memory test. VTS 2013: 1
2000 – 2009
- 2006
- [c11]Ramesh C. Tekumalla:
An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules. VLSI Design 2006: 824-827 - 2003
- [c10]Ramesh C. Tekumalla:
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures. ITC 2003: 737-744 - 2002
- [c9]Ramesh C. Tekumalla, Scott Davidson:
On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis. ITC 2002: 993-1002 - 2001
- [j2]Ramesh C. Tekumalla, Premachandran R. Menon:
Identification of primitive faults in combinational and sequentialcircuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1426-1442 (2001) - [c8]Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar:
On Diagnosing Path Delay Faults in an At-Speed Environment. VTS 2001: 28-33 - 2000
- [j1]Ramesh C. Tekumalla, Premachandran R. Menon:
On Redundant Path Delay Faults in Synchronous Sequential Circuits. IEEE Trans. Computers 49(3): 277-282 (2000) - [c7]Ramesh C. Tekumalla:
On Test Set Generation for Efficient Path Delay Fault Diagnosis. VTS 2000: 343-348
1990 – 1999
- 1999
- [c6]Ramesh C. Tekumalla, Premachandran R. Menon:
Robust testability of primitive faults using test points. ITC 1999: 260-268 - 1998
- [c5]Ramesh C. Tekumalla, Premachandran R. Menon:
On primitive fault test generation in non-scan sequential circuits. ICCAD 1998: 275-282 - 1997
- [c4]Ramesh C. Tekumalla, Premachandran R. Menon:
Test generation for primitive path delay faults in combinational circuits. ICCAD 1997: 636-641 - [c3]Ramesh C. Tekumalla, Premachandran R. Menon:
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. ICCD 1997: 648-653 - [c2]Ramesh C. Tekumalla, Premachandran R. Menon:
Delay Testing with Clock Control: An Alternative to Enhanced Scan. ITC 1997: 454-462 - 1996
- [c1]Ramesh C. Tekumalla, Premachandran R. Menon:
Identifying Redundant Path Delay Faults in Sequential Circuits. VLSI Design 1996: 406-411
Coauthor Index
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