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2020 – today
- 2021
[j1]Zhanwei Zhong
, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty:
Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 185-198 (2021)
2010 – 2019
- 2018
- [c6]Zhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty:
Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism. ITC 2018: 1-10 - [c5]Guoliang Li, Henry Zhao, Qinfu Yang, Jun Qian, Yu Huang:
Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures. ITC-Asia 2018: 109-114 - [c4]Zhanwei Zhong, Guoliang Li, Qinfu Yang, Jun Qian, Krishnendu Chakrabarty:
Broadcast-based minimization of the overall access time for the IEEE 1687 network. VTS 2018: 1-6 - 2015
- [c3]Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski:
Hybrid Hierarchical and Modular Tests for SoC Designs. NATW 2015: 11-16 - 2013
- [c2]Guoliang Li, Jun Qian, Yuan Zuo, Rui Li, Qinfu Yang:
Scan Test Data Volume Reduction for SoC Designs in EDT Environment. Asian Test Symposium 2013: 103-104
2000 – 2009
- 2009
- [c1]Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang:
Logic BIST Architecture for System-Level Test and Diagnosis. Asian Test Symposium 2009: 21-26
Coauthor Index
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