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Journal Articles
- 2021
[j32]Tomoaki Kawada
, Shinya Honda, Yutaka Matsubara, Hiroaki Takada:
TZmCFI: RTOS-Aware Control-Flow Integrity Using TrustZone for Armv8-M. Int. J. Parallel Program. 49(2): 216-236 (2021)- 2017
- [j31]Akihiro Yamaguchi, Yousuke Watanabe, Kenya Sato, Yukikazu Nakamoto, Yoshiharu Ishikawa, Shinya Honda, Hiroaki Takada:
In-vehicle Distributed Time-critical Data Stream Management System for Advanced Driver Assistance. J. Inf. Process. 25: 107-120 (2017) - 2015
- [j30]Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro:
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip. Inf. Media Technol. 10(3): 415-419 (2015) - [j29]Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro:
Automatic Synthesis of Inter-heterogeneous-processor Communication for Programmable System-on-chip. IPSJ Trans. Syst. LSI Des. Methodol. 8: 95-99 (2015) - [j28]Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro:
System-level Design Method for Control Systems with Hardware-implemented Interrupt Handler. J. Inf. Process. 23(5): 532-541 (2015) - 2014
- [j27]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. Inf. Media Technol. 9(1): 26-34 (2014) - [j26]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. IPSJ Trans. Syst. LSI Des. Methodol. 7: 37-45 (2014) - [j25]Yuki Ando, Masataka Ogawa, Yuya Mizoguchi, Kouta Kumagai, Miaw Torng-Der, Shinya Honda:
A Case Study of FPGA Blokus Duo Solver by System-Level Design. SIGARCH Comput. Archit. News 42(4): 57-62 (2014) - 2013
- [j24]Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, Hiroaki Takada:
Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. Int. J. Reconfigurable Comput. 2013: 789134:1-789134:40 (2013) - [j23]Daniel Sangorrín, Shinya Honda, Hiroaki Takada:
Reliable and Efficient Dual-OS Communications for Real-Time Embedded Virtualization. Inf. Media Technol. 8(1): 1-17 (2013) - [j22]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. Inf. Media Technol. 8(4): 924-928 (2013) - [j21]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. IPSJ Trans. Syst. LSI Des. Methodol. 6: 122-126 (2013) - 2012
- [j20]Kentaro Tomii, Yoshito Sawada, Shinya Honda:
Convergent evolution in structural elements of proteins investigated using cross profile analysis. BMC Bioinform. 13: 11 (2012) - [j19]Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada:
Comparison of Preemption Schemes for Partially Reconfigurable FPGAs. IEEE Embed. Syst. Lett. 4(2): 45-48 (2012) - [j18]Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs. IEICE Trans. Inf. Syst. 95-D(2): 345-353 (2012) - [j17]Daniel Sangorrín, Shinya Honda, Hiroaki Takada:
Integrated Scheduling for a Reliable Dual-OS Monitor. Inf. Media Technol. 7(2): 627-638 (2012) - [j16]Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
A Fast Performance Estimation Framework for System-Level Design Space Exploration. IPSJ Trans. Syst. LSI Des. Methodol. 5: 44-54 (2012) - 2010
- [j15]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 488-499 (2010) - [j14]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2509-2516 (2010) - [j13]Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation. Inf. Media Technol. 5(4): 1082-1096 (2010) - [j12]Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation. IPSJ Trans. Syst. LSI Des. Methodol. 3: 179-193 (2010) - 2009
- [j11]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. Inf. Media Technol. 4(4): 740-752 (2009) - [j10]Yoshito Sawada, Shinya Honda:
ProSeg: a database of local structures of protein segments. J. Comput. Aided Mol. Des. 23(3): 163-169 (2009) - [j9]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. J. Inf. Process. 17: 242-254 (2009) - 2008
- [j8]Masakazu Sekijima, Junta Doi, Shinya Honda, Tamotsu Noguchi, Shigenori Shimizu, Yutaka Akiyama:
Free Energy Landscape Analysis System Based on Parallel Molecular Dynamics Simulation. Inf. Media Technol. 3(1): 201-210 (2008) - [j7]Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada:
Embedded System Covalidation with RTOS Model and FPGA. Inf. Media Technol. 3(4): 739-743 (2008) - [j6]Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada:
Embedded System Covalidation with RTOS Model and FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 1: 126-130 (2008) - 2007
- [j5]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Function Call Optimization for Efficient Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(9): 2032-2036 (2007) - [j4]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2853-2862 (2007) - [j3]Masaki Yamamoto, Shinya Honda, Hiroaki Takada, Kiyoshi Agusa, Hiroyuki Tomiyama, Kenji Mase, Nobuo Kawaguchi, Nobuyuki Kaneko:
Practice and analysis of an extension course for training trainers of embedded software. SIGBED Rev. 4(1): 73-81 (2007) - 2005
- [j2]Hiroyuki Tomiyama, Shin-ichiro Chikada, Shinya Honda, Hiroaki Takada:
An RTOS-Based Design and Validation Methodology for Embedded Systems. IEICE Trans. Inf. Syst. 88-D(9): 2205-2208 (2005) - [j1]Masaki Yamamoto, Hiroyuki Tomiyama, Hiroaki Takada, Kiyoshi Agusa, Kenji Mase, Nobuo Kawaguchi, Shinya Honda, Nobuyuki Kaneko:
NEXCESS: Nagoya university extension courses for embedded software specialists. SIGBED Rev. 2(4): 20-24 (2005)
Conference and Workshop Papers
- 2019
- [c33]Shu Takemoto, Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa, Shinya Honda, Ryo Kurachi:
Performance Evaluation of CAESAR Authenticated Encryption on SROS2. AICCC 2019: 168-172 - [c32]Tomohiro Tsuruya, Musashi Danseko, Katsuhiko Sasaki, Shinya Honda, Ryo Takeda:
Process monitoring of deep drawing using machine learning. AIM 2019: 1227-1232 - [c31]Toki Matsumoto, Yukikazu Nakamoto, Ryota Yamamoto, Shinya Honda, Kazutoshi Wakabayashi:
Convolution Neural Network Development Support System using Approximation Methods to Evaluate Inference Accuracy and Memory Usage in an Embedded System. SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI 2019: 1312-1317 - 2018
- [c30]Masataka Ogawa, Shinya Honda, Hiroaki Takada:
Efficient Approach to Ensure Temporal Determinism in Automotive Control Systems. ISED 2018: 53-57 - [c29]Tasuku Ishigooka, Shinya Honda, Hiroaki Takada:
Cost-Effective Redundancy Approach for Fail-Operational Autonomous Driving System. ISORC 2018: 107-115 - 2017
- [c28]Kazuto Shigihara, Shinya Honda, Hiroaki Takada:
Test Program Generator for AUTOSAR OS. EDCC 2017: 79-86 - 2016
- [c27]Kunihiko Kaneko, Shinya Honda:
A Map Database System for Route Navigation with Multiple Transit Points and Destination Points. IIAI-AAI 2016: 219-223 - 2015
- [c26]Shinya Honda, Yoshihiro Narita, Naohiro Kida:
Adaptive control for vibration suppression by using self-organization map. ASCC 2015: 1-5 - [c25]Akihiro Yamaguchi, Yukikazu Nakamoto, Kenya Sato, Yoshiharu Ishikawa, Yousuke Watanabe, Shinya Honda, Hiroaki Takada:
AEDSMS: Automotive Embedded Data Stream Management System. ICDE 2015: 1292-1303 - 2014
- [c24]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs. FCCM 2014: 235 - [c23]Satoshi Katsunuma, Shinya Honda, Kenya Sato, Yousuke Watanabe, Yukikazu Nakamoto, Hiroaki Takada:
Real-Time-Aware Embedded DSMS Applicable to Advanced Driver Assistance Systems. SRDS Workshops 2014: 106-111 - [c22]Yukikazu Nakamoto, Akihiro Yamaguchi, Kenya Sato, Shinya Honda, Hiroaki Takada:
Toward Data-Centric Software Architecture for Automotive Systems - Embedded Data Stream Processing Approach. UIC/ATC/ScalCom 2014: 586-589 - 2013
- [c21]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration. IESS 2013: 171-180 - [c20]Yukikazu Nakamoto, Masanori Okamoto, Mohanmed Bhuiya, Akihiro Yamaguchi, Kenya Sato, Shinya Honda, Hiroaki Takada:
Android Platform Based on Vehicle Embedded Data Stream Processing. UIC/ATC 2013: 48-55 - 2012
- [c19]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis. HPCC-ICESS 2012: 1534-1540 - [c18]Yutaka Matsubara, Yasumasa Sano, Shinya Honda, Hiroaki Takada:
An Open-Source Flexible Scheduling Simulator for Real-Time Applications. ISORC 2012: 16-22 - [c17]Daniel Sangorrín, Shinya Honda, Hiroaki Takada:
Reliable Device Sharing Mechanisms for Dual-OS Embedded Trusted Computing. TRUST 2012: 74-91 - 2011
- [c16]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Fast design space exploration for mixed hardware-software embedded systems. ISOCC 2011: 92-95 - [c15]Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada:
Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems. ISOCC 2011: 183-186 - [c14]Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada:
Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. ReConFig 2011: 416-421 - 2010
- [c13]Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. DELTA 2010: 87-92 - [c12]Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems. FPL 2010: 352-355 - [c11]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Automatic communication synthesis with hardware sharing for design space exploration. ISCAS 2010: 1863-1866 - 2008
- [c10]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
CHStone: A benchmark program suite for practical C-based high-level synthesis. ISCAS 2008: 1192-1195 - 2007
- [c9]Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. ASP-DAC 2007: 336-341 - [c8]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. ACM Great Lakes Symposium on VLSI 2007: 365-370 - [c7]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. ICESS 2007: 261-270 - [c6]Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. ICESS 2007: 283-294 - 2006
- [c5]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Function Call Optimization in Behavioral Synthesis. DSD 2006: 522-529 - 2005
- [c4]Shin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Cosimulation of ITRON-based embedded software with SystemC. HLDVT 2005: 71-76 - 2004
- [c3]Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada:
RTOS-centric hardware/software cosimulator for embedded system design. CODES+ISSS 2004: 158-163 - 2003
- [c2]Shinya Honda, Hiroaki Takada:
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device. DATE 2003: 20138-20143 - [c1]Hiroaki Takada, Shinya Honda, Reiji Nishiyama, Hiroshi Yuyama:
Hardware/Software Co-Configuration for Multiprocessor SoPC. WSTFES 2003: 7-8
Parts in Books or Collections
- 2003
- [p1]Shinya Honda, Hiroaki Takada:
Evaluation of Applying SpecC to the Integrated Design Method of Device Driver and Device. Embedded Software for SoC 2003: 137-150
Coauthor Index
Yuko Hara-Azumi
aka: Yuko Hara
aka: Yuko Hara
[j32] [j31] [j30] [j29] [j28] [j27] [j26] [j24] [j23] [j22] [j21] [j19] [j18] [j17] [j16] [j15] [j14] [j13] [j12] [j11] [j9] [j7] [j6] [j5] [j4] [j3] [j2] [j1] [c30] [c29] [c28] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1] [p1]
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