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ORCIDMoslem Heidarpur
Person information
- affiliation: University of Windsor, Canada
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Books and Theses
- 2020
[b1]Moslem Heidarpur:
Spiking Neural Networks: Modification and Digital Implementation. University of Windsor, Ontario, Canada, 2020
Journal Articles
- 2024
- [j11]Madhan Thirumoorthi
, Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid:
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1423-1435 (2024) - 2023
- [j10]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
Digital Hardware Implementations of Spiking Neural Networks With Selective Input Sparsity for Edge Inferences in Controlled Image Acquisition Environments. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1724-1728 (2023) - [j9]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1377-1388 (2023) - [j8]Madhan Thirumoorthi, Alexander J. Leigh, Moslem Heidarpur, Mohammed A. S. Khalid, Mitra Mirhassani:
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1509-1522 (2023) - 2022
- [j7]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
A High-Accuracy Digital Implementation of the Morris-Lecar Neuron With Variable Physiological Parameters. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4138-4142 (2022) - [j6]Moslem Heidarpur, Mitra Mirhassani:
Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation". IEEE Trans. Very Large Scale Integr. Syst. 30(1): 112 (2022) - [j5]Madhan Thirumoorthi, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid:
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 30(5): 603-614 (2022) - 2021
- [j4]Moslem Heidarpur, Mitra Mirhassani:
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 667-676 (2021) - 2020
- [j3]Moslem Heidarpur, Parvin Khosravifar, Arash Ahmadi, Majid Ahmadi:
CORDIC-Astrocyte: Tripartite Glutamate-IP3-Ca2+ Interaction Dynamics on FPGA. IEEE Trans. Biomed. Circuits Syst. 14(1): 36-47 (2020) - 2019
- [j2]Moslem Heidarpur, Arash Ahmadi, Majid Ahmadi, Mostafa Rahimi Azghadi:
CORDIC-SNN: On-FPGA STDP Learning With Izhikevich Neurons. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(7): 2651-2661 (2019) - 2016
- [j1]Moslem Heidarpour, Arash Ahmadi, Rashid Rashidzadeh:
A CORDIC Based Digital Hardware For Adaptive Exponential Integrate and Fire Neuron. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1986-1996 (2016)
Conference and Workshop Papers
- 2023
- [c6]Edris Zaman Farsa, Moslem Heidarpur, Arash Ahmadi, Mitra Mirhassani:
High-Performance FPGA Implementation of Fully Connected Networks of SAM Neurons. ISCAS 2023: 1-5 - 2022
- [c5]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
Selective Input Sparsity in Spiking Neural Networks for Pattern Classification. ISCAS 2022: 799-803 - [c4]Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani:
A Low-Resource Digital Implementation of the Fitzhugh-Nagumo Neuron. PRIME 2022: 369-372 - 2020
- [c3]Moslem Heidarpur, Arash Ahmadi, Majid Ahmadi:
Time Step Impact on Performance and Accuracy of Izhikevich Neuron: Software Simulation and Hardware Implementation. ISCAS 2020: 1-5 - [c2]Moslem Heidarpur, Arash Ahmadi, Majid Ahmadi, Mostafa Rahimi Azghadi:
CORDIC-SNN: On-FPGA STDP Learning with Izhikevich Neurons. ISCAS 2020: 1 - 2019
- [c1]Moslem Heidarpur, Arash Ahmadi, Majid Ahmadi:
Digital Implementation of a Biological-Plausible Model for Astrocyte Ca ^2+ Oscillations. IWANN (2) 2019: 857-868
Informal and Other Publications
- 2025
- [i1]Moslem Heidarpur, Mitra Mirhassani, Norman Chang:
A Fully Pipelined FIFO Based Polynomial Multiplication Hardware Architecture Based On Number Theoretic Transform. CoRR abs/2501.11867 (2025)
Coauthor Index
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