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ORCIDJeffrey Stuecheli
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Journal Articles
- 2021
[j8]William J. Starke
, Brian W. Thompto, Jeffrey Stuecheli, José E. Moreira:
IBM's POWER10 Processor. IEEE Micro 41(2): 7-14 (2021)- 2018
- [j7]William J. Starke, J. S. Dodson, Jeffrey Stuecheli, Eric Retter, Brad W. Michael, Stephen J. Powell, James A. Marcella:
IBM POWER9 memory architectures for optimized systems. IBM J. Res. Dev. 62(4/5): 3:1-3:13 (2018) - [j6]Jeffrey Stuecheli, William J. Starke, John D. Irish, L. Baba Arimilli, Daniel M. Dreps, Bart Blaner, Curt Wollbrink, Brian Allison:
IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI. IBM J. Res. Dev. 62(4/5): 8:1-8:8 (2018) - 2015
- [j5]Balaram Sinharoy, Randal C. Swanberg, Naresh Nayar, Bruce G. Mealey, Jeffrey Stuecheli, Berni Schiefer, Jens Leenstra, Joefon Jann, P. Oehler, D. Levitan, S. Eisen, D. Sanner, Thomas Pflueger, Cédric Lichtenau, W. E. Hall, T. Block:
Advanced features in IBM POWER8 systems. IBM J. Res. Dev. 59(1) (2015) - [j4]William J. Starke, Jeffrey Stuecheli, David Daly, J. S. Dodson, Florian Auernhammer, Patricia Sagmeister, Guy L. Guthrie, Charles F. Marino, M. S. Siegel, Bart Blaner:
The cache and memory subsystems of the IBM POWER8 processor. IBM J. Res. Dev. 59(1) (2015) - [j3]Jeffrey Stuecheli, Bart Blaner, C. R. Johns, M. S. Siegel:
CAPI: A Coherent Accelerator Processor Interface. IBM J. Res. Dev. 59(1) (2015) - 2011
- [j2]Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John:
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue. IEEE Micro 31(1): 90-98 (2011) - 2002
- [j1]John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile:
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. IBM J. Res. Dev. 46(1): 53-76 (2002)
Conference and Workshop Papers
- 2021
- [c14]Guerney D. H. Hunt, Ramachandra Pai, Michael V. Le, Hani Jamjoom, Sukadev Bhattiprolu, Rick Boivie, Laurent Dufour, Brad Frey, Mohit Kapur, Kenneth A. Goldman, Ryan Grimm, Janani Janakirman, John M. Ludden, Paul Mackerras, Cathy May, Elaine R. Palmer, Bharata Bhasker Rao, Lawrence Roy, William A. Starke, Jeff Stuecheli, Enriquillo Valdez, Wendel Voigt:
Confidential computing for OpenPOWER. EuroSys 2021: 294-310 - [c13]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose:
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42 - 2019
- [c12]Jeff Stuecheli, Scott Willenborg, William J. Starke:
IBM's Next Generation POWER Processor. Hot Chips Symposium 2019: 1-19 - 2016
- [c11]Xing Liu, Daniele Buono, Fabio Checconi, Jee W. Choi, Xinyu Que, Fabrizio Petrini, John A. Gunnels, Jeff Stuecheli:
An Early Performance Study of Large-Scale POWER8 SMP Systems. IPDPS 2016: 263-272 - 2014
- [c10]Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor:
The POWER8TM processor: Designed for big data, analytics, and cloud environments. ICICDT 2014: 1-4 - 2013
- [c9]Jeff Stuecheli:
POWER8. Hot Chips Symposium 2013: 1-20 - [c8]Janani Mukundan, Hillery C. Hunter, Kyu-Hyoun Kim, Jeffrey Stuecheli, José F. Martínez:
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. ISCA 2013: 48-59 - 2011
- [c7]Dimitris Kaseridis, Muhammad Faisal Iqbal, Jeffrey Stuecheli, Lizy Kurian John:
MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches. PACT 2011: 205-206 - [c6]Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John:
Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era. MICRO 2011: 24-35 - 2010
- [c5]Dimitris Kaseridis, Jeffrey Stuecheli, Jian Chen, Lizy Kurian John:
A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems. HPCA 2010: 1-11 - [c4]Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John:
The virtual write queue: coordinating DRAM and last-level cache policies. ISCA 2010: 72-82 - [c3]Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John:
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory. MICRO 2010: 375-384 - 2009
- [c2]Dimitris Kaseridis, Jeffrey Stuecheli, Lizy K. John:
Bank-aware Dynamic Cache Partitioning for Multicore Architectures. ICPP 2009: 18-25 - 2006
- [c1]Robert H. Bell Jr., Rajiv R. Bhatia, Lizy K. John, Jeff Stuecheli, John Griswell, Paul Tu, Louis Capps, Anton Blanchard, Ravel Thai:
Automatic testcase synthesis and performance model validation for high performance PowerPC processors. ISPASS 2006: 154-165
Coauthor Index
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