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Eric Retter

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2010 – 2019

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2018
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  - journals/ibmrd/StarkeDSRMPM18
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William J. Starke, J. S. Dodson, Jeffrey Stuecheli, Eric Retter, Brad W. Michael, Stephen J. Powell, James A. Marcella:
IBM POWER9 memory architectures for optimized systems. IBM J. Res. Dev. 62(4/5): 3:1-3:13 (2018)

1990 – 1999

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1996
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Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter:
A parallel processing chip with embedded DRAM macros. IEEE J. Solid State Circuits 31(10): 1556-1559 (1996)
1995
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Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter:
Combined DRAM and logic chip for massively parallel systems. ARVLSI 1995: 4-16

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