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ORCIDSaroja V. Siddamal
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2020 – today
- 2024
[j3]Dharmaray Nedalgi, Saroja V. Siddamal
, S. S. Kerur:
2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues. Integr. 98: 102230 (2024)- 2023
- [c10]Dharmaray Nedalgi, Lavanya M. N, Saroja V. Siddamal:
Supply Noise and Peak Current Reduction in High-Speed Output Drivers. VLSID 2023: 127-132 - 2022
- [j2]Dharmaray Nedalgi, Saroja V. Siddamal:
Differential receiver with 2 × VDD input signals using 1 × VDD devices. Integr. 87: 306-312 (2022) - [j1]Dharmaray Nedalgi, Saroja V. Siddamal:
Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability. J. Circuits Syst. Comput. 31(11): 2250202:1-2250202:13 (2022) - 2021
- [c9]Dharmaray Nedalgi, Saroja V. Siddamal:
Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer. APCCAS 2021: 93-96 - [c8]Dharmaray Nedalgi, Saroja V. Siddamal:
$2 \times \text{VDD}$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability. APCCAS 2021: 97-100 - [c7]Dharmaray Nedalgi, Saroja V. Siddamal:
High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone. VLSID 2021: 135-138 - 2020
- [c6]Mandakini Kadam, Saroja V. Siddamal, Shripadraj Annigeri:
Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator. VDAT 2020: 1-5
2010 – 2019
- 2019
- [c5]Saroja V. Siddamal, Suhas B. Shirol, Shraddha Hiremath, Nalini C. Iyer:
Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology. VDAT 2019: 126-140 - [c4]Sachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Shraddha H, Saroja V. Siddamal, Sujata Kotabagi, Nalini C. Iyer:
Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter. VLSID 2019: 251-256 - 2018
- [c3]Akashaykumar H. Sunagar, Saroja V. Siddamal:
Development of Data Acquisition System using non-invasive Hardware and 3D software for Electric all terrain Vehicle. ICACCI 2018: 1212-1217 - 2014
- [c2]Narayan V. Sugur, Saroja V. Siddamal, Samba Sivam Vemala:
Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology. VLSID 2014: 353-358
2000 – 2009
- 2008
- [c1]Saroja V. Siddamal, R. M. Banakar, B. C. Jinaga:
Design of High-Speed Floating Point Multiplier. DELTA 2008: 285-289
Coauthor Index
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