![](https://dblp.uni-trier.de./img/logo.ua.320x120.png)
![](https://dblp.uni-trier.de./img/dropdown.dark.16x16.png)
![](https://dblp.uni-trier.de./img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
default search action
"Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ ..."
Dharmaray Nedalgi, Saroja V. Siddamal (2021)
- Dharmaray Nedalgi, Saroja V. Siddamal:
Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer. APCCAS 2021: 93-96
![](https://dblp.uni-trier.de./img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.