"Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ ..."

Dharmaray Nedalgi, Saroja V. Siddamal (2021)

> Home

Details and statistics

DOI: 10.1109/APCCAS51387.2021.9687738

access: closed

type: Conference or Workshop Paper

metadata version: 2022-02-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/apccas/NedalgiS21
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/apccas/NedalgiS21
Dharmaray Nedalgi, Saroja V. Siddamal:
Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer. APCCAS 2021: 93-96

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.