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Journal Articles
- 2015
[j6]Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. IEEE J. Solid State Circuits 50(6): 1372-1381 (2015)- 2013
- [j5]Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami
, Makoto Nagata:
Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. IEICE Trans. Electron. 96-C(6): 884-893 (2013) - 2012
- [j4]Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors. IEICE Trans. Electron. 95-C(1): 137-145 (2012) - 2011
- [j3]Yoji Bando, Makoto Nagata:
Microprocessor power noise measurements with different levels of resource occupancy. IEICE Electron. Express 8(3): 182-188 (2011) - [j2]Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. IEICE Trans. Electron. 94-C(4): 495-503 (2011) - [j1]Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. IEICE Trans. Electron. 94-C(6): 1024-1031 (2011)
Conference and Workshop Papers
- 2013
- [c3]Takashi Morie, Takuji Miki, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho:
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise. ISSCC 2013: 272-273 - 2011
- [c2]Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata:
Accurate analysis of substrate sensitivity of active transistors in an analog circuit. ISQED 2011: 56-61 - 2009
- [c1]Daisuke Kosaka, Yoji Bando, Goichi Yokomizo, Kunihiko Tsuboi, Ying Shiun Li, Shen Lin, Makoto Nagata:
A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design. CICC 2009: 219-222
Coauthor Index
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