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2020 – today
- 2024
[c23]Yu-Wei Huang, Cheng-En Wu, Wei-Bin Yang, Jen-Chieh Liu:
A Programmable DLL-based Delay Chain. ISOCC 2024: 29-30- [c22]Jiann-Chyi Rau, Wei-Bin Yang, Yu-Lung Lo, Chin-Yuan Shih, Cheng-Kai Lin, Che-Chia Chuang:
A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism. ISOCC 2024: 262-263 - [i2]Su-Xi Yu, Jing-Yuan He, Yi Wang, Yu-Jiao Cai, Jun Yang, Bo Lin, Wei-Bin Yang, Jian Ruan:
Texture Classification Network Integrating Adaptive Wavelet Transform. CoRR abs/2404.05300 (2024) - 2022
- [j14]Rui-Yang Ju
, Ting-Yu Lin, Jia-Hao Jian, Jen-Shiun Chiang, Wei-Bin Yang:
ThreshNet: An Efficient DenseNet Using Threshold Mechanism to Reduce Connections. IEEE Access 10: 82834-82843 (2022) - [j13]Wei-Bin Yang, Kuo-Ning Chang, Lu-Chun Yeh:
A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design. IEEE Syst. J. 16(3): 4222-4231 (2022) - [i1]Rui-Yang Ju, Ting-Yu Lin, Jia-Hao Jian, Jen-Shiun Chiang, Wei-Bin Yang:
ThreshNet: An Efficient DenseNet using Threshold Mechanism to Reduce Connections. CoRR abs/2201.03013 (2022) - 2021
- [j12]Wei-Bin Yang, Chi-Hsuan Sun, Diptendu Sinha Roy, Yi-Mei Chen:
Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input. IEEE Access 9: 157563-157570 (2021) - [j11]Shun Shen Peter Wang, Yin-Tien Wang, Choung-Lii Chao, Wei-Bin Yang:
Instrumentation of Twin-MCMs based mutual-test. Microelectron. J. 114: 105108 (2021) - [c21]Wei-Bin Yang, Shu-Yu Ku, Chun-Wei Wang, Li-Lun Chu:
Asynchronous Domino Binary search Digital LDO. ISPACS 2021: 1-2
2010 – 2019
- 2017
- [j10]Wei-Bin Yang, Yu-Yao Lin, Yu-Lung Lo:
Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input. Circuits Syst. Signal Process. 36(12): 5041-5061 (2017) - [j9]Wei-Bin Yang, Ming-Hao Hong, Jsung Mo Shen:
A Selectable Discrete-Voltage Output and Fast-Settling Low-Dropout Regulator Using Half Digitally-Assistant Voltage Accelerator. J. Signal Process. Syst. 89(2): 347-362 (2017) - 2016
- [j8]Wei-Bin Yang, Ming-Hao Hong:
A 25 MHz crystal less clock generator with background calibration against process and temperature variation. Comput. Electr. Eng. 52: 28-37 (2016) - 2015
- [c20]Wei-Bin Yang, Yu-Yao Lin, Chi-Hsiung Wang, Kuo-Ning Chang, Cing-Huan Chen, Yu-Lung Lo:
Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18µm CMOS process. ISPACS 2015: 57-61 - 2013
- [j7]Wei-Bin Yang, Chi-Hsiung Wang, Sheng-Shih Yeh, Chao-Cheng Liao:
A multiple frequency clock generator using wide operation frequency range phase interpolator. Microelectron. J. 44(8): 688-695 (2013) - [c19]Yu-Lung Lo, Jhih-Wei Tsai, Han-Ying Liu, Wei-Bin Yang:
A GHz full-division-range programmable divider with output duty-cycle improved. DDECS 2013: 82-85 - 2012
- [c18]Wei-Bin Yang, Chi-Hsiung Wang, I-Ting Chuo, Huang-Hsuan Hsu:
A 300 mV 10 MHz 4 kb 10T subthreshold SRAM for ultralow-power application. ISPACS 2012: 604-608 - 2011
- [j6]Wei-Bin Yang, Chao-Cheng Liao, Yung-Chih Liang:
A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process. Microelectron. J. 42(1): 43-51 (2011) - [j5]Wei-Bin Yang, Chang-Yo Hsieh:
A synthesizable pseudo fractional-N clock generator with improved duty cycle output. Microelectron. J. 42(10): 1099-1106 (2011) - [c17]Zheng-Yi Huang, Jen-Shiun Chiang, Wei-Bin Yang, Chi-Hsiung Wang:
A new temperature independent current controlled oscillator. ISPACS 2011: 1-4 - 2010
- [j4]Wei-Bin Yang, Yu-Lung Lo, Ting-Sheng Chao:
A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output. IEICE Trans. Electron. 93-C(3): 309-316 (2010)
2000 – 2009
- 2009
- [j3]Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng:
High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Trans. Electron. 92-C(6): 890-893 (2009) - [j2]Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng:
Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 339-343 (2009) - [c16]Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng:
0.5V 160-MHz 260uW all digital phase-locked loop. DDECS 2009: 186-193 - [c15]Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng:
Designing ultra-low voltage PLL Using a bulk-driven technique. ESSCIRC 2009: 388-391 - 2008
- [c14]Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw:
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS 2008: 64-67 - 2007
- [c13]Kuo-Hsing Cheng, Yu-Lung Lo, Ching-Wen Lai, Wei-Bin Yang:
A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique. ICECS 2007: 1163-1166 - [c12]Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien:
New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. ISCAS 2007: 3740-3743 - 2006
- [c11]Ting-Sheng Jau, Wei-Bin Yang, Chung-Yu Chang:
Analysis and Design of High Performance, Low Power Multiple Ports Register Files. APCCAS 2006: 1453-1456 - [c10]Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang:
A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay. ICECS 2006: 569-572 - [c9]Ting-Sheng Jau, Wei-Bin Yang, Yu-Lung Lo:
A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler. ICECS 2006: 902-905 - [c8]Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang:
The new improved pseudo fractional-N clock generator with 50% duty cycle. ISCAS 2006 - 2005
- [c7]Wei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng:
The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. ECCTD 2005: 193-196 - [c6]Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang:
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) 2005: 1174-1177 - 2004
- [c5]Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo:
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. ISCAS (1) 2004: 777-780 - 2003
- [j1]Kuo-Hsing Cheng, Wei-Bin Yang, Cheng-Ming Ying:
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 892-896 (2003) - 2001
- [c4]Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang, Wei-Bin Yang:
A difference detector PFD for low jitter PLL. ICECS 2001: 43-46 - [c3]Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, Shyh-Shyuan Sheu:
A CMOS low power voltage controlled oscillator with split-path controller. ICECS 2001: 421-424 - [c2]Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung:
A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) 2001: 614-617
1990 – 1999
- 1999
- [c1]Kuo-Hsing Cheng, Wei-Bin Yang:
The suggestion for CFS CMOS buffer. ICECS 1999: 799-802
Coauthor Index
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