"A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process."

Wei-Bin Yang, Chao-Cheng Liao, Yung-Chih Liang (2011)

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DOI: 10.1016/J.MEJO.2010.09.005

access: closed

type: Journal Article

metadata version: 2020-02-22

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Wei-Bin Yang, Chao-Cheng Liao, Yung-Chih Liang:
A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process. Microelectron. J. 42(1): 43-51 (2011)

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