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ORCIDShuhei Iwade
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2010 – 2019
- 2016
[c2]Ryota Bnadou, Masahiro Hiramori, Shuhei Iwade, Hiroshi Makino, Tutomu Yoshimura, Yoshio Matsuda:
A study on motion estimation algorithm for moving pictures. GCCE 2016: 1-3- [c1]Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda:
A study on fast motion estimation algorithm. GCCE 2016: 1-3 - 2014
- [j8]Shunji Nakata
, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2194-2203 (2014) - 2013
- [j7]Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda:
Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 896-907 (2013) - 2012
- [j6]Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. 6(4): 260-270 (2012) - 2011
- [j5]Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 230-234 (2011)
2000 – 2009
- 2004
- [j4]Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade:
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. IEEE J. Solid State Circuits 39(4): 684-693 (2004)
1990 – 1999
- 1999
- [j3]Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba:
The D30V/MPEG multimedia processor. IEEE Micro 19(4): 38-47 (1999) - 1995
- [j2]Koji Nii, Hideshi Maeno, Tokuya Osawa, Shuhei Iwade, Shinpei Kayano, Hiroshi Shibata:
A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates. IEEE J. Solid State Circuits 30(3): 316-320 (1995) - 1994
- [j1]Yoshiki Tsujihashi, Hisashi Matsumoto, Hidekatsu Nishimaki, Atsushi Miyanishi, Hiroomi Nakao, Osamu Kitada, Shuhei Iwade, Shinpei Kayano, Masayoshi Sakao:
A high-density data-path generator with stretchable cells. IEEE J. Solid State Circuits 29(1): 2-8 (1994)
Coauthor Index
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