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ORCIDNANOARCH 2018: Athens, Greece
- Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2018, Athens, Greece, July 17-19, 2018. ACM 2018, ISBN 978-1-4503-5815-6
- Michail Noltsis, Panayiotis Englezakis, Eleni Maragkoudaki, Chrysostomos Nicopoulos
, Dimitrios Rodopoulos, Francky Catthoor, Yiannakis Sazeides, Davide Zoni, Dimitrios Soudris:
Fast Estimations of Failure Probability Over Long Time Spans. 1-6 - Yuying Zhu, Weiqiang Liu, Jie Han, Fabrizio Lombardi:
A Probabilistic Error Model and Framework for Approximate Booth Multipliers. 7-12 - Manuel Escudero, Ioannis Vourkas, Antonio Rubio, Francesc Moll:
Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array. 13-18 - Mehrdad Biglari, Tobias Lieske, Dietmar Fey:
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States. 19-24 - Seyed Nima Mozaffari, Krishna Prasad Gnawali, Spyros Tragoudas:
An Aging Resilient Neural Network Architecture. 25-30 - Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil, Fadi J. Kurdahi:
Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning. 31-33 - Loai Danial, Shahar Kvatinsky:
Real-Time Trainable Data Converters for General Purpose Applications. 34-36 - Angelika Balliou, Jiri Pfleger, George Skoulatakis, Samrana Kazim, Jan Rakusan, Stella Kennou, Nikos Glezos:
Programmable Molecular-Nanoparticle Multi-junction Networks for Logic Operations. 37-43 - Konstantinos Rallis, Georgios Ch. Sirakoulis, Ioannis Karafyllidis, Antonio Rubio:
Multi-Valued Logic Circuits on Graphene Quantum Point Contact Devices. 44-48 - Vaibhav Vyas, Joseph S. Friedman:
Sequential Circuit Design with Bilayer Avalanche Spin Diode Logic. 49-50 - Yande Jiang, Nicoleta Cucu Laurenciu, Sorin Cotofana:
Complementary Arranged Graphene Nanoribbon-based Boolean Gates. 51-57 - Linbin Chen, Pilin Junsangsri, Pedro Reviriego, Fabrizio Lombardi:
CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems. 58-64 - Catherine E. Graves, Wen Ma, Xia Sheng, Brent Buchanan, Le Zheng, Sity Lam, Xuema Li, Sai Rahul Chalamalasetti, Lennie Kiyama, Martin Foltin, John Paul Strachan, Matthew P. Hardy:
Regular Expression Matching with Memristor TCAMs for Network Security. 65-71 - Chaoxin Ding, Wang Kang, He Zhang, Youguang Zhang, Weisheng Zhao:
A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation. 72-78 - Deming Zhang, Yanchun Hou, Chengzhi Wang, Jie Chen, Lang Zeng, Weisheng Zhao:
Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices. 79-85 - Orestis Liolis, Vassilios A. Mardiris, Georgios Ch. Sirakoulis, Ioannis G. Karafyllidis:
Quantum-dot Cellular Automata RAM design using Crossbar Architecture. 86-90 - Muhammed Ceylan Morgül, Onur Tunali, Mustafa Altun, Luca Frontini, Valentina Ciriani, Elena-Ioana Vatajelu, Lorena Anghel, Csaba Andras Moritz, Mircea R. Stan, Dan Alexandrescu:
Integrated Synthesis Methodology for Crossbar Arrays. 91-97 - Mohammed E. Fouda, Ahmed M. Eltawil, Fadi J. Kurdahi:
Minimal Disturbed Bits in Writing Resistive Crossbar Memories. 98-100 - Mihaela Malita, Gheorghe M. Stefan:
A Recursive Growing & Featuring Mechanism for Nanocomputing Structures. 101-106 - Amad Ul Hassen, Salman Anwar Khokhar, Haseeb Aslam Butt, Sumit Kumar Jha:
Free BDD based CAD of Compact Memristor Crossbars for in-Memory Computing. 107-113 - Naveen Kumar Macha, Sandeep Geedipally, Bhavana Tejaswini Repalle, Md Arif Iqbal, Wafi Danesh, Mostafizur Rahman:
Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits. 114-120 - Rajanikanth Desh, Naveen Kumar Macha, Sehtab Hossain, Repalle Bhavana Tejaswini, Mostafizur Rahman:
A Novel Analog to Digital Conversion Concept with Crosstalk Computing. 121-123 - Eleni Maragkoudaki, Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Energy Efficiency of Low Swing Signaling for Emerging Interposer Technologies. 124-130 - Reda Boumchedda, Jean-Philippe Noel, Bastien Giraud, Adam Makosiej, Marco Antonio Rios, Eduardo Esmanhotto, Emilien Bourde-Cicé, Mathis Bellet, David Turgis, Edith Beigné:
Energy-Efficient 4T SRAM Bitcell with 2T Read-Port for Ultra-Low-Voltage Operations in 28 nm 3D Monolithic CoolCubeTM Technology. 131-137 - Qin Li, Huifeng Zhu, Fei Qiao, Qi Wei, Xinjun Liu, Huazhong Yang:
Energy-efficient MFCC extraction architecture in mixed-signal domain for automatic speech recognition. 138-140 - Pratima Chatterjee, Prasun Ghosal:
Power Analysis of an mRNA-Ribosome System. 141-146 - Alexandru Paler:
Controlling distilleries in fault-tolerant quantum circuits: problem statement and analysis towards a solution. 147-152 - Vassilios A. Mardiris, Orestis Liolis, Georgios Ch. Sirakoulis, Ioannis G. Karafyllidis:
Signal Synchronization in Large Scale Quantum-dot Cellular Automata Circuits. 153-156 - Heinz Riener, Eleonora Testa, Luca G. Amarù, Mathias Soeken, Giovanni De Micheli:
Size Optimization of MIGs with an Application to QCA and STMG Technologies. 157-162 - Ioannis Karafyllidis, Georgios Ch. Sirakoulis, Panagiotis Dimitrakis:
Representation of Qubit States using 3D Memristance Spaces: A first step towards a Memristive Quantum Simulator. 163-168
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