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ORCID7th ISED 2017: Durgapur, India
- 7th International Symposium on Embedded Computing and System Design, ISED 2017, Durgapur, India, December 18-20, 2017. IEEE 2017, ISBN 978-1-5386-3032-7
- Samarjit Chakraborty
:
EDA for cyber-physical systems. 1-2 - Writam Banerjee, Ming Liu:
Three-dimensional emerging nonvolatile memory for the high-density and neuromorphic applications. 1-5 - Anupam Chattopadhyay, Kwok-Yan Lam:
Security of autonomous vehicle as a cyber-physical system. 1-6 - Sinam Ajitkumar Singh, Abhishek Verma, Shuvam Chhetry, Swanirbhar Majumder:
Abnormality analysis of pcg signal using vmd and mlp neural network. 1-5 - Kunal Khade, Revati Naik, Amey Patil:
Design of all color line follower sensor with auto calibration ability. 1-5 - Moumita Das, Ansuman Banerjee, Bhaskar Sardar:
An empirical study on performance of branch predictors with varying storage budgets. 1-5 - Sudeep Ghosh, Surajit Kumar Roy, Hafizur Rahaman, Chandan Giri:
TSV repairing for 3D ICs using redundant TSV. 1-5 - Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee:
K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction. 1-5 - Ankita Samaddar, Moumita Das, Ansuman Banerjee:
A new memory scheduling policy for real time systems. 1-4 - Nikita Gupta, Pragati Thakur, Shashank Kumar Dubey, Aminul Islam:
Design of nonvolatile MRAM bitcell. 1-4 - Rohan Mukherjee, Anupam Banerjee, Indrajit Chakrabarti, Pranab Kumar Dutta, Ajoy Kumar Ray:
Efficient VLSI design of CAVLC decoder of H.264 for HD videos. 1-4 - B. Dinesh Kumar, Sumit Pandey, Puneet Arora, Rahul Shrestha:
A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector. 1-5 - Parth Shah, Kanniganti Abhishek, Soumya J.:
Fault-tolerant application specific Network-on-Chip design. 1-5 - Mrinal Goswami, Aron Narzary, Govind Raj, Bibhash Sen:
Design of reversible bidirectional logarithmic barrel shifter. 1-4 - Avishek Choudhury, Biplab K. Sikdar:
CIFR: A complete in-place fault remapping strategy for CMP cache using dynamic reuse distance. 1-5 - Pranab Roy, Amiya Sahoo, Hafizur Rahaman:
Adaptive medical detection system: An iterative averaging method for automated detection analysis using DMFBs. 1-6 - Fritjof Bornebusch, Robert Wille, Rolf Drechsler:
Towards lightweight satisfiability solvers for self-verification. 1-5 - Bhaskar Mondal, Tarni Mandal, Punj Kumar, Neel Biswas:
A secure partial encryption scheme based on bit plane manipulation. 1-5 - Don Kurian Dennis, Ayushi Priyam, Sukhpreet Singh Virk, Sajal Agrawal, Tanuj Sharma, Arijit Mondal, Kailash Chandra Ray:
Single cycle RISC-V micro architecture processor and its FPGA prototype. 1-5 - Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar:
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000. 1-6 - Priyanandini Das, Pranose J. Edavoor, Sithara Raveendran, Sunil Rathore, Amol D. Rahulkar:
Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA. 1-6 - Sharbani Purkayastha, Shyamapada Mukherjee:
Lookahead legalization based global placement for heterogeneous FPGAs. 1-5 - Sabyasachee Banerjee, Subhashis Majumder, Abhishek Varma, Debesh K. Das:
A placement optimization technique for 3D IC. 1-5 - Jaishree Mayank, Arijit Mondal:
Non-preemptive multiprocessor scheduling for periodic real-time tasks. 1-6 - Deepa Mathew, Bijoy Antony Jose:
Performance analysis of virtualized embedded computing systems. 1-5 - Naween Kumar, Dinesh Dash:
Maximum data gathering through speed control of path-constrained mobile sink in WSN. 1-4 - Sourav Das, Mayuree Shegaonkar, Mrityunjay Gupta, Parimal Acharjee:
Optimal placement of UPFC across a transmission line considering techno-economic aspects with physical limitation. 1-5 - Sandeep Raj, Kailash Chandra Ray:
Application of variational mode decomposition and ABC optimized DAG-SVM in arrhythmia analysis. 1-5 - Atma Ram Gupta:
Effect of optimal allocation of multiple DG and D-STATCOM in radial distribution system for minimizing losses and THD. 1-5 - Pushpita Roy, Ansuman Banerjee:
Security assessment of synthesized actuation sequences for digital microfluidic biochips. 1-4 - Atul Kumar Dwivedi, Sandeep Kumar Bhatt, Subhojit Ghosh:
Fractional order butterworth filter design using Artificial Bee colony algorithm. 1-5 - Alisha Oraon, Shradha Shreya, Renuka Kumari, Aminul Islam:
A double trench 4H - SiC MOSFET as an enhanced model of SiC UMOSFET. 1-5 - Soumyajit Poddar, Suraj, Amit Kumar Yadav, Hafizur Rahaman:
OTORNoC: Optical tree of rings network on chip for 1000 core systems. 1-5 - Ganapathi Hegde, K. Srinivasa Reddy, T. K. Ramesh:
An approach for area and power optimization of flipping 3-D discrete wavelet transform architecture. 1-5 - Rupam Das, Kaustav Mallick, Tunisha Tanvi, Kanishka Sah:
Voltage mode universal filter design using CCDDCCTA. 1-4 - Meelu Padhi, Ravindra Chaudhari:
An optimized pipelined architecture of SHA-256 hash function. 1-4 - Ankur Pokhara, Jatin Agrawal, Biswajit Mishra:
Design of an all-digital, low power time-to-digital converter in 0.18μm CMOS. 1-5 - Arpan Manna, Subham Saha, Rakesh Das, Chandan Bandyopadhyay, Hafizur Rahaman:
All optical design of cost efficient multiplier circuit using terahertz optical asymmetric demultiplexer. 1-5 - Bappaditya Mondal, Chandan Bandyopadhyay, Hafizur Rahaman:
Detection and localization of appearance faults in reversible circuits. 1-5 - Umang Agarwal:
Multirotor performance optimization using genetic algorithm. 1-5 - Moumita Chakraborty, Debasri Saha, Amlan Chakrabarti:
A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage. 1-4 - Archana Bhat, V. Geetha:
Survey on routing protocols for Internet of Things. 1-5 - Mrinal Goswami, Mohit Kumar, Bibhash Sen:
Cost effective realization of XOR logic in QCA. 1-5 - Teressa Longjam, Dakshina Ranjan Kisku:
A supervised manipuri offline signature verification system with global and local features. 1-6
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