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ORCIDSithara Raveendran
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2020 – today
- 2023
[c10]Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran:
Approximate Three-Operand Binary Adder for Error-Resilient Applications. iSES 2023: 287-291- 2022
- [c9]Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha:
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. ISCAS 2022: 3428-3432 - 2021
- [j5]Sithara Raveendran
, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha:
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access 9: 108119-108130 (2021) - [j4]Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar:
Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications. J. Circuits Syst. Comput. 30(8): 2150138:1-2150138:27 (2021) - 2020
- [j3]Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar:
Approximate Multiplier Design Using Novel Dual-Stage 4: 2 Compressors. IEEE Access 8: 48337-48351 (2020) - [j2]Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha:
An Approximate Low-Power Lifting Scheme Using Reversible Logic. IEEE Access 8: 183367-183377 (2020) - [j1]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
Design and implementation of image kernels using reversible logic gates. IET Image Process. 14(16): 4110-4121 (2020) - [c8]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha:
Reversible Logic Implementation of Image Denoising for Grayscale Images. MWSCAS 2020: 138-141
2010 – 2019
- 2019
- [c7]Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B.:
Design and Analysis of Energy Efficient Reversible Logic based Full Adder. MWSCAS 2019: 339-342 - 2018
- [c6]Sampada Barve, Sithara Raveendran, Charudatta Korde, Trilochan Panigrahi, Nithin Y. B. Kumar, M. H. Vasantha:
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics. iSES 2018: 6-10 - [c5]Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha:
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. TENCON 2018: 1813-1817 - 2017
- [c4]Priyanandini Das, Pranose J. Edavoor, Sithara Raveendran, Sunil Rathore, Amol D. Rahulkar:
Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA. ISED 2017: 1-6 - [c3]Pranose J. Edavoor, Sithara Raveendran, Amol D. Rahulkar:
Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000. ISED 2017: 1-6 - 2016
- [c2]Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha:
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. ICCCNT 2016: 35:1-35:6 - [c1]A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha:
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. VLSID 2016: 202-206
Coauthor Index
aka: Nithin Y. B. Kumar
aka: Nithin Kumar Y. B.
aka: Kumar Y. B. Nithin
aka: Y. B. Nithin Kumar
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