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ORCIDSunil Rathore
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2020 – today
- 2024
[c5]Sunil Rathore, Navjeet Bagga, S. Dasgupta:
Self-Heating and Process-Induced Threshold Voltage Aware Reliability and Aging Analysis of Forksheet FET. IRPS 2024: 65- 2023
- [j4]Sunil Rathore, Rajeewa Kumar Jaisawal
, Pravin Neminath Kondekar, Navjeet Bagga:
Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET. Microelectron. J. 139: 105904 (2023) - [c4]Navneet Gandhi, Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Ankit Dixit, Naveen Kumar, Vihar P. Georgiev, Navjeet Bagga:
Gate Oxide Induced Reliability Assessment of Junctionless FinFET-Based Hydrogen Gas Sensor. SENSORS 2023: 1-4 - [c3]Sunil Rathore, Rajeewa Kumar Jaisawal, P. N. Kondekar, Navneet Gandhi, Shashank Banchhor, Young Suh Song, Navjeet Bagga:
Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET. IRPS 2023: 1-5 - 2022
- [j3]Rajeewa Kumar Jaisawal, P. N. Kondekar, Sameer Yadav, Pranshoo Upadhyay, Bhaskar Awadhiya, Sunil Rathore:
Insights into the operation of negative capacitance FinFET for low power logic applications. Microelectron. J. 119: 105321 (2022) - [j2]Sunil Rathore, Rajeewa Kumar Jaisawal, Navneet Gandhi, P. N. Kondekar, Navjeet Bagga:
Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor. Microelectron. J. 129: 105590 (2022) - [j1]Toushik Santra, Ankit Dixit, Rajeewa Kumar Jaisawal, Sunil Rathore, Saheli Sarkhel, Navjeet Bagga:
Investigation of geometrical impact on a P+ buried negative capacitance SOI FET. Microelectron. J. 130: 105617 (2022) - [c2]Rajeewa Kumar Jaisawal, Sunil Rathore, P. N. Kondekar, Navjeet Bagga:
Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α). VDAT 2022: 97-106
2010 – 2019
- 2017
- [c1]Priyanandini Das, Pranose J. Edavoor, Sithara Raveendran, Sunil Rathore, Amol D. Rahulkar:
Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA. ISED 2017: 1-6
Coauthor Index
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