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Publication search results
found 18 matches
- 2017
- Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Yasmin Afsharnezhad, Elham Zahraie Salehi:
CL-CPA: A hybrid carry-lookahead/carry-propagate adder for low-power or high-performance operation mode. Integr. 57: 62-68 (2017) - Ahmad Rahati Belabad, Seyed Ahmad Motamedi, Saeed Sharifian:
An adaptive digital predistortion for compensating nonlinear distortions in RF power amplifier with memory effects. Integr. 57: 184-191 (2017) - George Charitopoulos, Iosif Koidis, Kyprianos Papadimitriou, Dionisios N. Pnevmatikatos:
Run-time management of systems with partially reconfigurable FPGAs. Integr. 57: 34-44 (2017) - Hongmei Chen, Yunsheng Pan, Yongsheng Yin, Fujiang Lin:
All-digital background calibration technique for timing mismatch of time-interleaved ADCs. Integr. 57: 45-51 (2017) - Masumeh Damghanian, Seyed Javad Azhari:
A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications. Integr. 57: 158-168 (2017) - Libao Deng, Baoquan Zhang, Sha Wang, Chengyu Jin:
IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs. Integr. 57: 132-146 (2017) - Ganesh Kumar Ganjikunta, Subhendu Kumar Sahoo:
An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications. Integr. 57: 125-131 (2017) - Maede Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit. Integr. 57: 11-19 (2017) - Jui-Hung Hsieh, Jian-Hao Huang, Hung-Ren Wang:
DVFS-aware motion estimation design scheme based on bandwidth-rate-distortion optimization in application processor systems. Integr. 57: 74-80 (2017) - Jie Jin:
Resonant amplifier-based sub-harmonic mixer for zero-IF transceiver applications. Integr. 57: 69-73 (2017) - Deokjin Joo, Taewhan Kim:
Clock buffer polarity assignment under useful skew constraints. Integr. 57: 52-61 (2017) - Ahmet Kakacak, Aydin Emre Guzel, Ozan Cihangir, Sezer Gören, H. Fatih Ugurdag:
Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression. Integr. 57: 147-157 (2017) - Rajit Karmakar, Santanu Chattopadhyay:
Temperature and data size trade-off in dictionary based test data compression. Integr. 57: 20-33 (2017) - Jaeyoung Kim, Pinaki Mazumder:
A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS. Integr. 57: 1-10 (2017) - Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue:
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. Integr. 57: 108-124 (2017) - Navid Rahmanikia, Amirali Amiri, Hamid Noori, Farhad Mehdipour:
Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor. Integr. 57: 81-100 (2017) - Andreas Tsimpos, Andreas Christos Demartinos, Spyridon Vlassis, George Souliotis:
Jitter tolerance calibration for high-speed serial interfaces. Integr. 57: 101-107 (2017) - Michael A. Turi, José G. Delgado-Frias:
Full-VDD and near-threshold performance of 8T FinFET SRAM cells. Integr. 57: 169-183 (2017)
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