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Publication search results
found 26 matches
- 1997
- Vishwani D. Agrawal:
Editorial. J. Electron. Test. 10(1-2): 5 (1997) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 10(3): 171 (1997) - Minesh B. Amin, Bapiraju Vinnakota:
Workload Distribution in Fault Simulation. J. Electron. Test. 10(3): 277-282 (1997) - Michael L. Bushnell, John Giraldi:
A Functional Decomposition Method for Redundancy Identification and Test Generation. J. Electron. Test. 10(3): 175-195 (1997) - Debaleena Das, Mark G. Karpovsky:
Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations. J. Electron. Test. 10(3): 215-229 (1997) - René David, Janusz A. Brzozowski, Helmut Jürgensen:
Testing for Bounded Faults in RAMs. J. Electron. Test. 10(3): 197-214 (1997) - Michele Favalli, Marcello Dalpasso
:
Symbolic Handling of Bridging Fault Effects. J. Electron. Test. 10(3): 271-276 (1997) - Andrew Flint:
MCM Test Strategy Synthesis from Chip Test and Board Test Approaches. J. Electron. Test. 10(1-2): 65-76 (1997) - Anne E. Gattiker, Wojciech Maly:
Smart Substrate MCMs. J. Electron. Test. 10(1-2): 39-53 (1997) - Larry Gilg:
Known Good Die. J. Electron. Test. 10(1-2): 15-25 (1997) - Najmi T. Jarwala:
Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules. J. Electron. Test. 10(1-2): 77-86 (1997) - Joel A. Jorgenson, Russell J. Wagner:
Design-For-Test in a Multiple Substrate Multichip Module. J. Electron. Test. 10(1-2): 97-107 (1997) - Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. J. Electron. Test. 10(3): 255-269 (1997) - Cynthia F. Murphy, Magdy S. Abadir, Peter Sandborn:
Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die. J. Electron. Test. 10(1-2): 151-166 (1997) - Prawat Nagvajara, J. Lin, P. Nilagupta, C. Wang:
Multichip Module Diagnosis by Product-Code Signatures. J. Electron. Test. 10(1-2): 127-136 (1997) - Ken Posse:
A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules. J. Electron. Test. 10(1-2): 119-125 (1997) - C. P. Ravikumar, Nitin Agrawal, Parul Agarwal:
Hierarchical Delay Test Generation. J. Electron. Test. 10(3): 231-244 (1997) - Jacob Savir:
Delay Test Generation: A Hardware Perspective. J. Electron. Test. 10(3): 245-254 (1997) - Jacob Savir:
Module Level Weighted Random Patterns. J. Electron. Test. 10(3): 283-287 (1997) - Ralf Schmid, Reinhold Schmitt, Matthias Brunner, Oliver Gessner, Matthias Sturm:
Electron Beam Probing - A Solution for MCM Test and Failure Analysis. J. Electron. Test. 10(1-2): 55-63 (1997) - Thomas M. Storey, Bruce McWilliam:
A Test Methodology for High Performance MCMs. J. Electron. Test. 10(1-2): 109-118 (1997) - Madhavan Swaminathan, Bruce C. Kim, Abhijit Chatterjee:
A Survey of Test Techniques for MCM Substrates. J. Electron. Test. 10(1-2): 27-38 (1997) - Mick Tegethoff, Tom Chen:
Simulation Techniques for the Manufacturing Test of MCMs. J. Electron. Test. 10(1-2): 137-149 (1997) - Yervant Zorian:
Guest Editorial. J. Electron. Test. 10(1-2): 6 (1997) - Yervant Zorian:
Fundamentals of MCM Testing and Design-for-Testability. J. Electron. Test. 10(1-2): 7-14 (1997) - Yervant Zorian, Hakim Bederr:
An Effective Multi-Chip BIST Scheme. J. Electron. Test. 10(1-2): 87-95 (1997)
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retrieved on 2024-08-07 23:11 CEST from data curated by the dblp team
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