• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 55 matches

• 2024
• 
  Junchao Chen, Giuseppe Esposito, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Angeliki Kritikakou, Milos Krstic, Robert Limas Sierra, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Marcello Traiola, Alessandro Veronesi:
  Reliability Assessment of Large DNN Models: Trading Off Performance and Accuracy. VLSI-SoC 2024: 1-10
• 
  Seema G. Aarella, Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos:
  Fortified-Edge 5.0: Federated Learning for Secure and Reliable PUF in Authentication Systems. VLSI-SoC 2024: 1-6
• 
  Ayushi Agarwal, Radhika Dharwadkar, Isaar Ahmad, Krishna Kumar, P. J. Joseph, Sourav Roy, Prokash Ghosh, Preeti Ranjan Panda:
  APPAMM: Memory Management for IPsec Application on Heterogeneous SoCs. VLSI-SoC 2024: 1-6
• 
  Bulbul Ahmed, Sujan Kumar Saha, Jingbo Zhou, Sohrab Aftabjahani, Mark M. Tehranipoor, Farimah Farahmandi:
  Continuity in Security: Leveraging LLM for Translating Security Properties Across Hardware Designs. VLSI-SoC 2024: 1-6
• 
  Lilas Alrahis, Mohammed Thari Nabeel, Johann Knechtel, Ozgur Sinanoglu:
  The Impact of Logic Synthesis and Technology Mapping on Logic Locking Security. VLSI-SoC 2024: 1-6
• 
  Sami El Amraoui, Régis Leveugle, Paolo Maistri:
  Capture the Pulse: Impact of FPGA Resource Utilization on EM Fault Injection Attacks Detection. VLSI-SoC 2024: 1-6
• 
  Asmae El Arrassi, Mohammad Amin Yaldagard, Xingjian Tao, Taha Shahroodi, Fouwad Jamil Mir, Yashvardhan Biyani, Manil Dev Gomony, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui:
  AFSRAM-CIM: Adder Free SRAM-Based Digital Computation-in-Memory for BNN. VLSI-SoC 2024: 1-6
• 
  Mouadh Ayache, Enkele Rama, Saleh Mulhem, Mladen Berekovic, Matthias Korb:
  Holistic Framework for Evaluating the Trustworthiness of Integrated Circuits. VLSI-SoC 2024: 1-4
• 
  Mario Barbareschi, Salvatore Barone, Antonio Emmanuele, Nicola Mazzocca:
  Exploiting Functional Approximation on Decision-Tree Based Multiple Classifier Systems. VLSI-SoC 2024: 1-4
• 
  Venkata K. V. V. Bathalapalli, Aakarshan Kumar, Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka:
  BlockShield: A TPM-Integrated Blockchain-Based Framework for Shielding Against Deepfakes. VLSI-SoC 2024: 1-6
• 
  Abhiroop Bhowmik, Subin Babukutty, Mottaqiallah Taouil, Moritz Fieback:
  A Unified Functional Safety EDA Framework for Accurate Diagnostic Coverage Estimation. VLSI-SoC 2024: 1-6
• 
  Mujahid Bilal, M. Kamran Bhatti, Muhammad Kahsif Minhas, Haroon Waris:
  Design Co-Processor Based on Partially Homomorphic Encryption Execution Using Open-Source Tool. VLSI-SoC 2024: 1-4
• 
  Bram Van Bolderik, Vlado Menkovski, Sonia Heemstra, Manil Dev Gomony:
  MEAN: Mixture-of-Experts Based Neural Receiver. VLSI-SoC 2024: 1-4
• 
  Ernesto Cristopher Villegas Castillo, Felipe Augusto da Silva, Michael Glaß:
  Diagnostic Coverage Estimation for Automotive SoCs Based on Colored Stochastic Petri Nets. VLSI-SoC 2024: 1-6
• 
  Natalia Cherezova, Salvatore Pappalardo, Mahdi Taheri, Mohammad Hasan Ahmadilivani, Bastien Deveautour, Alberto Bosio, Jaan Raik, Maksim Jenihhin:
  Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability. VLSI-SoC 2024: 1-4
• 
  Jiteshri Dasari, Cunxi Yu, Maciej J. Ciesielski:
  Linear Algebra Approach to Verification of Modular $(2{n}-1)$ Multipliers. VLSI-SoC 2024: 1-6
• 
  Assia El-Hadbi, Oussama Elissati, Laurent Fesquet:
  Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation. VLSI-SoC 2024: 1-4
• 
  Rafaella Elia, Theocharis Theocharides:
  Embedded and Real-Time Anomalous Command Classification in Unmanned Ground Vehicle Operations. VLSI-SoC 2024: 1-6
• 
  Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn:
  A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology. VLSI-SoC 2024: 1-5
• 
  Uxua Esteban-Eraso, Carlos Sánchez-Azqueta, Francisco Aznar, Concepción Aldea, Santiago Celma:
  Compensating the Load Effect in Quadrature All-Pass Filters. VLSI-SoC 2024: 1-4
• 
  Anis Fellah-Touta, Lilian Bossuet, Vincent Grosso, Carlos Andres Lara-Nino:
  Lightweight Active Fences for FPGAs. VLSI-SoC 2024: 1-4
• 
  Istvan Andras Gergely, Sebastian Rausch, Nahla A. El-Araby, Axel Jantsch:
  Resource Management of Automotive Engine Control Units. VLSI-SoC 2024: 1-4
• 
  Paulette Iskandar, Bryan Olmos, Wolfgang Kunz, Djones Lettnin:
  Adaptable FWHW Formal Co-Verification of SoC RISC-V Components. VLSI-SoC 2024: 1-6
• 
  Mohammad Ismael, Ayman Hroub, Nasib Naser:
  SystemVerilog-SystemC TestBench Architecture for VLSI Chip Design Verification. VLSI-SoC 2024: 1-4
• 
  Esrat Khan, Shahzad Muzaffar, Lamees M. Al Qassem, Ibrahim M. Elfadel:
  OSHDA: A Containerized CAD Tool for the Design and Analysis of Behavioral FSM Logic Locking. VLSI-SoC 2024: 1-6
• 
  Sumanth Kolluru, Kenneth S. Stevens:
  Behavioral Simulation of Relative Timed Asynchronous Circuits. VLSI-SoC 2024: 1-6
• 
  Rishabh Mahanta, Hemangee K. Kapoor:
  DynaCache: A Checkpoint Aware Reconfigurable Cache for Intermittently Powered Computing Systems. VLSI-SoC 2024: 1-6
• 
  Thomas Makryniotis, Georgi Gaydadjiev, Said Hamdioui, Mottaqiallah Taouil:
  Multi-Level FeFET-Based CAM Address Decoder. VLSI-SoC 2024: 1-6
• 
  Sara Mannaa, Cédric Marchand, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Christoph Lenz, Oskar Baumgartner, Ian O'Connor:
  3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis. VLSI-SoC 2024: 1-4
• 
  Muhammad Kashif Minhas, Haroon Waris, Sajid Baloch:
  FVDCLS: Functional Verification of RISCV Based Dual-Core Lockstep Feature Using Fault Injection Mechanism. VLSI-SoC 2024: 1-4

skipping 25 more matches