• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 14 matches

• 2017
• 
  François Abel, Andreas Doering:
  Microserver + micro-switch = micro-datacenter. AISTECS@HiPEAC 2017: 3
• 
  Marco Balboni, Davide Bertozzi:
  Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels. AISTECS@HiPEAC 2017: 12-17
• 
  Kari Clark, Phill Watt:
  Enabling high performance rack-scale optical switching through global synchronisation. AISTECS@HiPEAC 2017: 4
• 
  Monobrata Debnath, Dimitris Konstantinou, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos, Wei-Ming Lin, Junghee Lee:
  Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling. AISTECS@HiPEAC 2017: 8-11
• 
  Benoît Dupont de Dinechin, Amaury Graillat:
  Network-on-chip service guarantees on the kalray MPPA-256 bostan processor. AISTECS@HiPEAC 2017: 35-40
• 
  Yong Hu, Daniel Müller-Gritschneder, Ulf Schlichtmann:
  Model-based framework for networks-on-chip design space exploration. AISTECS@HiPEAC 2017: 32-35
• 
  Muhammad Obaidullah, Gul N. Khan:
  Optimal application mapping to 2D-mesh NoCs by using a tabu-based particle swarm methodology. AISTECS@HiPEAC 2017: 17-22
• 
  Emmanuel Ofori-Attah, Michael Opoku Agyeman:
  A survey of low power NoC design techniques. AISTECS@HiPEAC 2017: 22-27
• 
  Jean-Pierre Panziera:
  BXI: designing a network for eXascale. AISTECS@HiPEAC 2017: 2
• 
  Fernando Pereñíguez-Garcia, José L. Abellán:
  Secure communications in wireless network-on-chips. AISTECS@HiPEAC 2017: 27-32
• 
  Nikos Pleros, Nikos Terzenidis, Theoni Alexoudi, K. Vyrsokinos, George T. Kanellos, Dimitris Syrivelis:
  Software-defined board- and chip-level optical interconnects for multi-socket communication and disaggregated computing. AISTECS@HiPEAC 2017: 6-7
• 
  Syed Ijlal Shah:
  Interconnects for next generation SoC designs. AISTECS@HiPEAC 2017: 1
• 
  Jeremiah J. Wilke:
  Bringing minimal routing back to HPC through silicon photonics: a study of "flexfly" architectures with the structural simulation toolkit (SST). AISTECS@HiPEAC 2017: 5
• 
  Sören Sonntag, José Manuel García Carrasco, José Luis Abellán Miguel, Daniel Müller-Gritschneder:
  Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2017, Stockholm, Sweden, January 25, 2017. ACM 2017, ISBN 978-1-4503-5226-0 [contents]