• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 25 matches

• 2015
• 
  Guillaume Berhault, Camille Leroux, Christophe Jégo, Dominique Dallet:
  Hardware implementation of a soft cancellation decoder for polar codes. DASIP 2015: 1-8
• 
  Jens Brandenburg, Benno Stabernack:
  Exploring the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi core architectures. DASIP 2015: 1-8
• 
  Mourad Dridi, Mohamed Mourad Hafidhi, Chris Winstead, Emmanuel Boutillon:
  Reliable NCO carrier generators for GPS receivers. DASIP 2015: 1-5
• 
  Mohamed Mourad Hafidhi, Emmanuel Boutillon, Chris Winstead:
  Reducing the impact of internal upsets inside the correlation process in GPS Receivers. DASIP 2015: 1-5
• 
  Julien Hascoet, Jean-François Nezan, Andrew Ensor, Benoît Dupont de Dinechin:
  Implementation of a Fast Fourier transform algorithm onto a manycore processor. DASIP 2015: 1-7
• 
  Amina El Hassen, Aymeric Histace, Mehdi Terosiet, Olivier Romain:
  FPGA-based detection of QRS complexes in ECG signal. DASIP 2015: 1-7
• 
  Sebastian Hesselbarth, Gregor Schewior, Holger Blume:
  Fast and accurate power estimation for application-specific instruction set processors using FPGA emulation. DASIP 2015: 1-7
• 
  Ercan Kalali, Ilker Hamzaoglu:
  FPGA implementations of HEVC Inverse DCT using high-level synthesis. DASIP 2015: 1-6
• 
  Mateusz Komorkiewicz, Tomasz Kryjak, Katarzyna Chuchacz-Kowalczyk, Pawel Skruch, Marek Gorgon:
  FPGA based system for real-time structure from motion computation. DASIP 2015: 1-7
• 
  Jordane Lorandel, Jean-Christophe Prévotet, Maryline Hélard:
  Dynamic power evaluation of LTE wireless baseband processing on FPGA. DASIP 2015: 1-6
• 
  Kevin J. M. Martin, Yvan Eustache, Jean-Philippe Diguet, Thanh Dinh Ngo, Emmanuel Casseau, Yaset Oliva:
  Compa backend: A dynamic runtime for the execution of dataflow programs onto multi-core platforms. DASIP 2015: 1-2
• 
  Maurizio Masera, Lorenzo Re Fiorentin, Maurizio Martina, Guido Masera, Enrico Masala:
  Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding. DASIP 2015: 1-6
• 
  Paolo Meloni, Giuseppe Tuveri, Danilo Pani, Luigi Raffo, Francesca Palumbo:
  Exploring custom heterogeneous MPSoCs for real-time neural signal decoding. DASIP 2015: 1-8
• 
  Sajjad Nouri, Waqar Hussain, Jari Nurmi:
  Implementation of IEEE-802.11a/g receiver blocks on a coarse-grained reconfigurable array. DASIP 2015: 1-8
• 
  Andrianiaina Ravelomanantsoa, Hassan Rabah, Amar Rouane:
  Fast and efficient signals recovery for deterministic compressive sensing: Applications to biosignals. DASIP 2015: 1-6
• 
  Marc Reichenbach, Maximilian Kasparek, Mohammad Alawieh, Konrad Häublein, Dietmar Fey:
  Real-time correlation for locating systems utilizing heterogeneous computing architectures. DASIP 2015: 1-8
• 
  Jens Rettkowski, David Gburek, Diana Göhringer:
  Robot navigation based on an efficient combination of an extended A∗ algorithm, bird's eye view and image stitching. DASIP 2015: 1-8
• 
  Sampsa Sarjanoja, Jani Boutellier, Jari Hannuksela:
  BM3D image denoising using heterogeneous computing platforms. DASIP 2015: 1-8
• 
  Vítor Schwambach, Sébastien Cleyet-Merle, Alain Issard, Stéphane Mancini:
  Image tiling for embedded applications with non-linear constraints. DASIP 2015: 1-8
• 
  Mladen Skelin, Marc Geilen, Francky Catthoor, Sverre Hendseth:
  Worst-case latency analysis of SDF-based parametrized dataflow MoCs. DASIP 2015: 1-6
• 
  Benno Stabernack, Jan Moller, Jan Hahlbeck, Jens Brandenburg:
  Demonstrating an FPGA implementation of a full HD real-time HEVC decoder with memory optimizations for range extensions support. DASIP 2015: 1-2
• 
  Shanshan Wang, Chenglong Xiao, Wanjun Liu, Emmanuel Casseau, Xiao Yang:
  Selecting most profitable instruction-set extensions using ant colony heuristic. DASIP 2015: 1-7
• 
  Guy Wassi, Sylvain Iloga, Olivier Romain, Bertrand Granado:
  FPGA-based real-time MFCC extraction for automatic audio indexing on FM broadcast data. DASIP 2015: 1-6
• 
  Stephan Werner, Bernhard Stiehle, Jürgen Becker:
  Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip. DASIP 2015: 1-6
• 
  2015 Conference on Design and Architectures for Signal and Image Processing, DASIP 2015, Krakow, Poland, September 23-25, 2015. IEEE 2015, ISBN 978-1-4673-7738-6 [contents]