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found 26 matches

• 1997
• 
  Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt:
  Two-Phase Asynchronous Pipeline Control. ASYNC 1997: 12-23
• 
  Wendy Belluomini, Chris J. Myers:
  Efficient Timing Analysis Algorithms for Timed State Space Exploration. ASYNC 1997: 88-100
• 
  Supratik Chakraborty, David L. Dill:
  More Accurate Polynomial-Time Min-Max Timing Simulation. ASYNC 1997: 112-
• 
  Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun:
  Timing Analysis of Extended Burst-Mode Circuits. ASYNC 1997: 101-111
• 
  Jo C. Ebergen, Robert Berks:
  Response Time Properties of Some Asynchronous Circuits. ASYNC 1997: 76-
• 
  Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, Paul Day, N. C. Paver:
  AMULET2e: An Asynchronous Embedded Controller. ASYNC 1997: 290-
• 
  D. A. Gilbert, Jim D. Garside:
  A Result Forwarding Mechanism for Asynchronous Pipelined Systems. ASYNC 1997: 2-11
• 
  David A. Kearney, Neil W. Bergmann:
  Bundled Data Asynchronous Multipliers with Data Dependent Computation Times. ASYNC 1997: 186-197
• 
  Joep L. W. Kessels, Paul Marston:
  Designing Asynchronous Standby Circuits for a Low-Power Pager. ASYNC 1997: 268-278
• 
  Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev:
  Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. ASYNC 1997: 240-253
• 
  Paul G. Lucassen, Indra Polak, Jan Tijmen Udding:
  Normal Form in DI-Algebra with Recursion. ASYNC 1997: 167-174
• 
  Willem C. Mallon, Jan Tijmen Udding:
  Using Metrics for Proof Rules for Recursively Defined Delay-insensitive Specifications. ASYNC 1997: 175-
• 
  Riccardo Mariani, Roberto Roncella, Roberto Saletti, Pierangelo Terreni:
  On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic. ASYNC 1997: 54-
• 
  Gensoh Matsubara, Nobuhiro Ide:
  A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit. ASYNC 1997: 198-209
• 
  Pedro A. Molina, Peter Y. K. Cheung:
  A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. ASYNC 1997: 126-139
• 
  Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau:
  A FIFO Ring Performance Experiment. ASYNC 1997: 279-289
• 
  Steven M. Nowick, Kenneth Y. Yun, Ayoob E. Dooply, Peter A. Beerel:
  Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders. ASYNC 1997: 210-
• 
  Peggy B. K. Pang, Mark R. Greenstreet:
  Self-Timed Meshes Are Faster Than Synchronous. ASYNC 1997: 30-
• 
  Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell:
  Delay Insensitive Logic for RSFQ Superconductor Technology. ASYNC 1997: 42-53
• 
  O. A. Petlin, Stephen B. Furber:
  Built-In Self-Testing of Micropipelines. ASYNC 1997: 22-29
• 
  Juha Plosila, Kaisa Sere:
  Action Systems in Pipelined Processor Design. ASYNC 1997: 156-166
• 
  J. W. J. M. Rutten, Michel R. C. M. Berkelaar:
  Improved State Assignment for Burst Mode Finite State Machines. ASYNC 1997: 228-239
• 
  Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella, Luciano Lavagno:
  Partial order based approach to synthesis of speed-independent circuits. ASYNC 1997: 254-
• 
  Aiguo Xie, Peter A. Beerel:
  Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events. ASYNC 1997: 64-75
• 
  Kenneth Y. Yun, Ayoob E. Dooply, Julio Arceo, Peter A. Beerel, Vida Vakilotojar:
  The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver. ASYNC 1997: 140-
• 
  3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands. IEEE Computer Society 1997, ISBN 0-8186-7922-0 [contents]