- Amir Momeni, Hamed Tabkhi, Yash Ukidave, Gunar Schirner, David R. Kaeli:
Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA. SIGARCH Comput. Archit. News 43(4): 52-57 (2015) - Koji Okina, Rie Soejima, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri:
Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization. SIGARCH Comput. Archit. News 43(4): 9-14 (2015) - Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav Sedukhin:
Stream Computation of Shallow Water Equation Solver for FPGA-based 1D Tsunami Simulation. SIGARCH Comput. Archit. News 43(4): 82-87 (2015) - Mark Thorson:
Internet Nuggets. SIGARCH Comput. Archit. News 43(2): 10-16 (2015) - Mark Thorson:
Internet Nuggets. SIGARCH Comput. Archit. News 43(4): 94-100 (2015) - Mark Thorson:
Internet Nuggets. SIGARCH Comput. Archit. News 43(5): 7-11 (2015) - Da Tong, Viktor K. Prasanna:
High Throughput Sketch Based Online Heavy Hitter Detection on FPGA. SIGARCH Comput. Archit. News 43(4): 70-75 (2015) - Chiharu Tsuruta, Yohei Miki
, Takuya Kuhara, Hideharu Amano, Masayuki Umemura:
Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters. SIGARCH Comput. Archit. News 43(4): 3-8 (2015) - Xinying Wang, Phillip H. Jones, Joseph Zambreno:
A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns. SIGARCH Comput. Archit. News 43(4): 76-81 (2015) - 2014
- Yuki Ando, Masataka Ogawa, Yuya Mizoguchi, Kouta Kumagai, Miaw Torng-Der, Shinya Honda:
A Case Study of FPGA Blokus Duo Solver by System-Level Design. SIGARCH Comput. Archit. News 42(4): 57-62 (2014) - Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, Michael M. Swift:
BadgerTrap: a tool to instrument x86-64 TLB misses. SIGARCH Comput. Archit. News 42(2): 20-23 (2014) - Diana Göhringer:
Reconfigurable Multiprocessor Systems: Handling Hydras Heads - A Survey. SIGARCH Comput. Archit. News 42(4): 39-44 (2014) - Mioara Joldes, Valentina Popescu, Warwick Tucker:
Searching for Sinks for the Hénon Map using a Multipleprecision GPU Arithmetic Library. SIGARCH Comput. Archit. News 42(4): 63-68 (2014) - Yuetsu Kodama, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato:
PEACH2: An FPGA-based PCIe network device for Tightly Coupled Accelerators. SIGARCH Comput. Archit. News 42(4): 3-8 (2014) - Jean-Louis Lafitte:
Entangled-Coupling. SIGARCH Comput. Archit. News 42(5): 7-15 (2014) - Takuji Mitsuishi, Shimpei Nomura, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano:
Accelerating Breadth First Search on GPU-BOX. SIGARCH Comput. Archit. News 42(4): 81-86 (2014) - Subijit Mondal, Subhashis Maitra:
Data security-modified AES algorithm and its applications. SIGARCH Comput. Archit. News 42(2): 1-8 (2014) - Shin Morishima, Hiroki Matsutani:
Performance Evaluations of Graph Database using CUDA and OpenMP Compatible Libraries. SIGARCH Comput. Archit. News 42(4): 75-80 (2014) - Atin Mukherjee, Amitabha Sinha, Debesh Choudhury:
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation. SIGARCH Comput. Archit. News 42(5): 1-6 (2014) - Shimpei Nomura, Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano:
Performance Analysis of the Multi-GPU System with ExpEther. SIGARCH Comput. Archit. News 42(4): 9-14 (2014) - José L. Núñez-Yáñez:
Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling. SIGARCH Comput. Archit. News 42(4): 87-92 (2014) - Kentaro Sano, Ryotaro Chiba, Tomoya Ueno, Hayato Suzuki, Ryo Ito, Satoru Yamamoto:
FPGA-based Custom Computing Architecture for Large-Scale Fluid Simulation with Building Cube Method. SIGARCH Comput. Archit. News 42(4): 45-50 (2014) - Soumik Sen, Subhashis Maitra:
Three levels three dimensional compact coding. SIGARCH Comput. Archit. News 42(2): 9-14 (2014) - Rie Soejima, Koji Okina, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri:
A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis. SIGARCH Comput. Archit. News 42(4): 69-74 (2014) - Yu Tanabe, Tsutomu Maruyama:
Fast and Accurate Optical Flow Estimation using FPGA. SIGARCH Comput. Archit. News 42(4): 27-32 (2014) - Alexander Thomasian, Bingxing Liu, Yuhui Deng:
Balancing disk access times in RAID5 disk arrays in degraded mode by conditionally prioritizing fork/join requests. SIGARCH Comput. Archit. News 42(2): 15-19 (2014) - Mark Thorson:
Internet nuggets. SIGARCH Comput. Archit. News 42(2): 24-36 (2014) - Mark Thorson:
Internet Nuggets. SIGARCH Comput. Archit. News 42(4): 93-101 (2014) - Mark Thorson:
Internet Nuggets. SIGARCH Comput. Archit. News 42(5): 16-25 (2014) - César Torres-Huitzil, Marco Aurelio Nuño-Maganda:
Areatime Efficient Implementation of Local Adaptive Image Thresholding in Reconfigurable Hardware. SIGARCH Comput. Archit. News 42(4): 33-38 (2014)
