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2020 – today
- 2022
[j17]Atri Sanyal
, Amitabha Sinha:
Trans_Proc: A Reconfigurable Processor to Implement The Linear Transformations. Int. J. Softw. Innov. 10(1): 1-16 (2022)
2010 – 2019
- 2015
- [i4]Atin Mukherjee, Amitabha Sinha, Debesh Choudhury:
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation. CoRR abs/1502.07055 (2015) - 2014
- [j16]Atin Mukherjee, Amitabha Sinha, Debesh Choudhury:
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation. SIGARCH Comput. Archit. News 42(5): 1-6 (2014) - 2013
- [j15]Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty:
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays. SIGARCH Comput. Archit. News 41(2): 1-8 (2013) - [j14]Amrita Saha, Manideepa Mukherjee, Debanjana Datta, Sangita Saha, Amitabha Sinha:
Performance analysis of a FPGA based novel binary and DBNS multiplier. SIGARCH Comput. Archit. News 41(2): 9-16 (2013) - [j13]Amrita Saha, Pijush Biswas, Amitabha Sinha:
An integrated development platform of a reconfigurable radio processor for software defined radio. SIGARCH Comput. Archit. News 41(2): 30-35 (2013) - [j12]Santanu Pal, Amitabha Sinha, Pijush Biswas:
FPGA implementation of a novel DCT architecture reducing constant cosine terms. SIGARCH Comput. Archit. News 41(2): 36-40 (2013) - [j11]Subhashis Maitra, Amitabha Sinha:
High performance MAC unit for DSP and cryptographic applications. SIGARCH Comput. Archit. News 41(2): 47-55 (2013) - [j10]Subhashis Maitra, Amitabha Sinha:
High efficiency MAC unit used in digital signal processing and elliptic curve cryptography. SIGARCH Comput. Archit. News 41(4): 1-7 (2013) - [j9]Subhashis Maitra, Amitabha Sinha:
Design and simulation of MAC unit using combinational circuit and adder. SIGARCH Comput. Archit. News 41(5): 25-33 (2013) - [i3]Amitabha Sinha, Soumojit Acharyya, Suranjan Chakraborty, Mitrava Sarkar:
Field Programmable DSP Arrays - A. CoRR abs/1305.3251 (2013) - [i2]Amitabha Sinha, Mitrava Sarkar, Soumojit Acharyya, Suranjan Chakraborty:
A Novel Reconfigurable Architecture of a DSP Processor for Efficient Mapping of DSP Functions using Field Programmable DSP Arrays. CoRR abs/1306.0089 (2013) - 2012
- [j8]Nishant Kumar Giri, Amitabha Sinha:
FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT. SIGARCH Comput. Archit. News 40(2): 28-32 (2012) - [j7]Aniruddha Ghosh, Satrughna Singha, Amitabha Sinha:
A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system. SIGARCH Comput. Archit. News 40(2): 33-38 (2012) - [j6]Aniruddha Ghosh, Satrughna Singha, Amitabha Sinha:
"Floating point RNS": a new concept for designing the MAC unit of digital signal processor. SIGARCH Comput. Archit. News 40(2): 39-43 (2012) - [j5]Subhashis Maitra, Amitabha Sinha:
A new algorithm for computing triple-base number system. SIGARCH Comput. Archit. News 40(4): 3-9 (2012) - [c3]Chaitali Biswas Dutta, Partha Garai, Amitabha Sinha:
A Scheme for Improving Bit Efficiency for Residue Number System. ACITY (3) 2012: 649-656 - [i1]Chaitali Biswas Dutta, Partha Garai, Amitabha Sinha:
Design Of A Reconfigurable DSP Processor With Bit Efficient Residue Number System. CoRR abs/1211.5248 (2012) - 2011
- [j4]Malay Das, Amitabha Sinha, Nishant Kumar Giri:
High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA). SIGARCH Comput. Archit. News 39(5): 1-4 (2011) - [j3]Anindita Chakraborty, Amitabha Sinha:
Conversion of binary to single-term triple base numbers for DSP applications. SIGARCH Comput. Archit. News 39(5): 5-11 (2011) - [j2]Satrughna Singha, Aniruddha Ghosh, Amitabha Sinha:
A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique. SIGARCH Comput. Archit. News 39(5): 12-18 (2011) - 2010
- [j1]Manideepa Mukherjee, Amitabha Sinha:
A novel architecture for conversion of binary to single digit double base numbers. SIGARCH Comput. Archit. News 38(5): 1-6 (2010) - [c2]Sharbari Banerjee, Amitabha Sinha:
A reconfigurable Digital Signal Processor using residue number system. ISSPA 2010: 405-408
2000 – 2009
- 2009
- [c1]Amrita Saha, Amitabha Sinha:
An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio. ICETC 2009: 45-49
Coauthor Index
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