- 2009
- Andrea Acquaviva, Nicola Bombieri
, Franco Fummi, Sara Vinco:
Automatic customization of device drivers for IP-cores used with assorted CPU organizations. CODES+ISSS 2009: 173-182 - Jason Agron, David Andrews:
Building heterogeneous reconfigurable systems with a hardware microkernel. CODES+ISSS 2009: 393-402 - Shirish Bahirat, Sudeep Pasricha:
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. CODES+ISSS 2009: 129-136 - Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula:
A scalable parallel H.264 decoder on the cell broadband engine architecture. CODES+ISSS 2009: 353-362 - Lars Bauer, Muhammad Shafique, Jörg Henkel:
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. CODES+ISSS 2009: 335-342 - Paul Bogdan, Radu Marculescu:
Statistical physics approaches for network-on-chip traffic characterization. CODES+ISSS 2009: 461-470 - Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A high-level virtual platform for early MPSoC software development. CODES+ISSS 2009: 11-20 - Jason Cong, Albert Liu, Bin Liu:
A variation-tolerant scheduler for better than worst-case behavioral synthesis. CODES+ISSS 2009: 221-228 - Alireza Ejlali, Bashir M. Al-Hashimi, Petru Eles:
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems. CODES+ISSS 2009: 193-202 - Deepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann:
Fast model-based test case classification for performance analysis of multimedia MPSoC platforms. CODES+ISSS 2009: 413-422 - Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
TotalProf: a fast and accurate retargetable source code profiler. CODES+ISSS 2009: 305-314 - Patrice Gerin, Mian Muhammad Hamayun, Frédéric Pétrot:
Native MPSoC co-simulation environment for software performance estimation. CODES+ISSS 2009: 403-412 - Mohammad Ali Ghodrat, Tony Givargis:
Efficient dynamic voltage/frequency scaling through algorithmic loop transformation. CODES+ISSS 2009: 203-210 - Marius Gligor, Nicolas Fournel, Frédéric Pétrot:
Using binary translation in event driven simulation for fast and flexible MPSoC simulation. CODES+ISSS 2009: 71-80 - Rodrígo González-Alberquilla, Fernando Castro, Luis Piñuel, Francisco Tirado:
Stack oriented data cache filtering. CODES+ISSS 2009: 257-266 - Andreas Hansson, Kees Goossens:
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. CODES+ISSS 2009: 99-108 - Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran:
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. CODES+ISSS 2009: 295-304 - Xin He, Jorgen Peddersen, Sri Parameswaran:
LOP: a novel SRAM-based architecture for low power and high throughput packet classification. CODES+ISSS 2009: 137-146 - Yongsoo Joo, Youngjin Cho, Kyungsoo Lee, Naehyuck Chang:
Improving application launch times with hybrid disks. CODES+ISSS 2009: 373-382 - Heekyung Kim, Dukyoung Yun, Soonhoi Ha:
Scalable and retargetable simulation techniquesfor multiprocessor systems. CODES+ISSS 2009: 89-98 - Glenn Leary, Karam S. Chatha:
Automated technique for design of NoC with minimal communication latency. CODES+ISSS 2009: 471-480 - Yangsup Lee, Sanghyuk Jung, Yong Ho Song:
FRA: a flash-aware redundancy array of flash storage devices. CODES+ISSS 2009: 163-172 - Weichen Liu, Zonghua Gu, Jiang Xu, Yu Wang, Mingxuan Yuan:
An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking. CODES+ISSS 2009: 61-70 - Yi-Len Lo, Mao Lin Li, Ren-Song Tsay:
Cycle count accurate memory modeling in system level design. CODES+ISSS 2009: 287-294 - Ya-Shuai Lü, Li Shen, Zhiying Wang, Nong Xiao:
Dynamically utilizing computation accelerators for extensible processors in a software approach. CODES+ISSS 2009: 51-60 - Martin Lukasiewycz, Michael Glaß, Jürgen Teich:
Exploiting data-redundancy in reliability-aware networked embedded system design. CODES+ISSS 2009: 229-238 - Martin Lukasiewycz, Michael Glaß, Jürgen Teich, Paul Milbredt:
FlexRay schedule optimization of the static segment. CODES+ISSS 2009: 363-372 - Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128 - Sjoerd Meijer, Hristo Nikolov, Todor P. Stefanov:
On compile-time evaluation of process partitioning transformations for Kahn process networks. CODES+ISSS 2009: 31-40 - Arslan Munir, Ann Gordon-Ross:
An MDP-based application oriented optimal policy for wireless sensor networks. CODES+ISSS 2009: 183-192
