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ORCIDMartine D. F. Schlag
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- affiliation: University of California, Santa Cruz, USA
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Journal Articles
- 2000
[j16]Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie:
Distributed-memory parallel routing for field-programmable gatearrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 850-862 (2000)- 1999
- [j15]Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan:
Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1389-1399 (1999) - 1996
- [j14]Martine D. F. Schlag, F. Joel Ferguson:
Detection of Multiple Faults in Two-Dimensional ILAs. IEEE Trans. Computers 45(6): 741-746 (1996) - [j13]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral-based multiway FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 554-560 (1996) - 1994
- [j12]Martine D. F. Schlag, Jackson Kong, Pak K. Chan:
Routability-driven technology mapping for lookup table-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 13-26 (1994) - [j11]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral K-way ratio-cut partitioning and clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1088-1096 (1994) - 1993
- [j10]Richard Anderson, Simon Kahan, Martine D. F. Schlag:
Single-Layer Cylindrical Compaction. Algorithmica 9(3): 293-312 (1993) - [j9]Martine D. F. Schlag, Pak K. Chan, Jackson Kong:
Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 713-722 (1993) - 1992
- [j8]Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson
, Vojin G. Oklobdzija:
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. IEEE Trans. Computers 41(8): 920-930 (1992) - 1990
- [j7]Pak K. Chan, Martine D. F. Schlag:
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. IEEE Trans. Computers 39(8): 983-992 (1990) - 1989
- [j6]Pak K. Chan, Martine D. F. Schlag:
Bounds on signal delay in RC mesh networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(6): 581-589 (1989) - 1987
- [j5]Ying-Fung Wu, Peter Widmayer, Martine D. F. Schlag, C. K. Wong:
Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles. IEEE Trans. Computers 36(3): 321-331 (1987) - 1986
- [j4]Peter Widmayer, Ying-Fung Wu, Martine D. F. Schlag, Chak-Kuen Wong:
On some union and intersection problems for polygons with fixed orientations. Computing 36(3): 183-197 (1986) - 1985
- [j3]Martine D. F. Schlag, Ellen J. Yoffa, Peter S. Hauge, Chak-Kuen Wong:
A Method for Improving Cascode-Switch Macro Wirability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(2): 150-155 (1985) - 1984
- [j2]Martine D. F. Schlag, Lin S. Woo, Chak-Kuen Wong:
Maximizing pin alignment by pin permutations. Integr. 2(4): 279-307 (1984) - 1983
- [j1]Martine D. F. Schlag, Yuh-Zen Liao, C. K. Wong:
An algorithm for optimal two-dimensional compaction of VLSI layouts. Integr. 1(2-3): 179-209 (1983)
Conference and Workshop Papers
- 2003
- [c15]Pak K. Chan, Martine D. F. Schlag:
Parallel placement for field-programmable gate arrays. FPGA 2003: 43-50 - 2000
- [c14]Pak K. Chan, Martine D. F. Schlag:
New parallelization and convergence results for NC: a negotiation-based FPGA router. FPGA 2000: 165-174 - 1997
- [c13]Pak K. Chan, Martine D. F. Schlag:
Acceleration of an FPGA router. FCCM 1997: 175-181 - [c12]Jason Y. Zien, Pak K. Chan, Martine D. F. Schlag:
Hybrid spectral/iterative partitioning. ICCAD 1997: 436-440 - 1996
- [c11]Jason Y. Zien, Martine D. F. Schlag, Pak K. Chan:
Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. ICCAD 1996: 201-204 - 1995
- [c10]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral-Based Multi-Way FPGA Partitioning. FPGA 1995: 133-139 - 1993
- [c9]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
On Routability Prediction for Field-Programmable Gate Arrays. DAC 1993: 326-330 - [c8]Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral K-Way Ratio-Cut Partitioning and Clustering. DAC 1993: 749-754 - 1992
- [c7]Martine D. F. Schlag, Jackson Kong, Pak K. Chan:
Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. ICCD 1992: 86-90 - 1991
- [c6]Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija:
Delay optimization of carry-skip adders and block carry-lookahead adders. IEEE Symposium on Computer Arithmetic 1991: 154-164 - 1989
- [c5]Pak K. Chan, Martine D. F. Schlag:
Analysis and design of CMOS Manchester adders with variable carry-skip. IEEE Symposium on Computer Arithmetic 1989: 86-95 - [c4]Richard Anderson, Simon Kahan, Martine D. F. Schlag:
An O(n log n) algorithm for 1-D tile compaction. ICCAD 1989: 144-147 - [c3]Richard Anderson, Simon Kahan, Martine D. F. Schlag:
An O(n log n) Algorithm for 1-D Tile Compaction. WG 1989: 287-301 - 1987
- [c2]Martine D. F. Schlag:
The planar topology of functional programs. FPCA 1987: 174-193 - 1985
- [c1]Dorab Patel, Martine D. F. Schlag, Milos D. Ercegovac:
vFP: An Environment for the Multi-level Specification, Analysis, and Synthesis of Hardware Algorithms. FPCA 1985: 238-255
Editorship
- 2002
- [e2]Martine D. F. Schlag, Steve Trimberger:
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002. ACM 2002, ISBN 1-58113-452-5 [contents] - 2001
- [e1]Scott Hauck, Martine D. F. Schlag, Russell Tessier:
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001. ACM 2001, ISBN 1-58113-341-3 [contents]
Coauthor Index
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